一种用于并行处理器系统的通用数据传输控制单元

Y. Nakakura, K. M. Sameky, Y. Tue, I. Okabayashi, M. Nakajima, S. Karino, K. Kaneko, H. Kadota
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引用次数: 3

摘要

1. 介绍了VLSl并行pmwss系统是未来机器进行重型数值计算的重要支柱之一。对于并联系统。要实现高性能,不仅要保证处理器单元的运行速度,还要保证pe间的数据传输。尤其是。在具有局部存储器和连接网络的并行处理器系统中。有两个主要问题:“如何在不受PE操作干扰的情况下实现本地存储器之间的快速数据传输”和“如何在本地存储器中分配数据”。开发了一种新的VLSI控制器,用于高性能并行处理器系统:ADENAUI的多功能数据传输控制。chtp对硬件提出的问题给出了一些答案。在本文中。介绍了TCU的结构和工作原理,以及专用地址块地址生成器的电路。本文还讨论了chlp布局技术。
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A versatile data-transfer control unit for a parallel processor system
1. Intrdudirm VLSl parallel pmwssor system Is one of pmmlslng candldates for the future machine to carry out heavy-duty numerlcal computation. For the parallel system. not only PElprocessor element) operation speed but also Inter-PE data transfer Is very Important to achleve high performance. Especially. in the parallel processor system with localized memories and a connection network. there are two malor questions : "haw to realize emcient data transfer between local memories wlth mlnlmum lnterference wlth PE operatlons." and "how to assign the data In local memories? A new VLSI controller has been dmloped as a versatile data-transfcr control unR, X U , In a hlgh-prrfmmancc parallel pmccsor system : ADENAUI. The chtp gives some answers to the questions by the hardware. In this paper. the archltecture and the operations of TCU and the circults far the dedicated addrwslng block Address Generator are cxplalned. The chlp layout techniques are also discussed.
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