{"title":"将场效应管布局验证系统扩展到双极技术","authors":"J. Gannett","doi":"10.1109/BIPOL.1988.51074","DOIUrl":null,"url":null,"abstract":"Rink, an automatic layout verification system intended for FET technologies, has been enhanced to handle bipolar designs. A straightforward procedure that uses Rink's parasitic capacitance extractor to solve the bipolar device identification problem is described. The bipolar enhancements to Rink have been used successfully on a set of seven high-speed bipolar chips designed for lightwave communication. These chips ranged in complexity from 23 to 67 devices. Full-custom, nonmanhattan layouts for these chips were created on polygon-pusher style layout editors. For each chip, Rink executed an automatic comparison of the netlist extracted from the layout against a SPICE reference netlist. The latter has been coded for SPICE design simulations. Several fatal connectivity errors were uncovered as were a few significant disparities in resistor values and transistor sizes.<<ETX>>","PeriodicalId":302949,"journal":{"name":"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Extending an FET layout verification system to bipolar technology\",\"authors\":\"J. Gannett\",\"doi\":\"10.1109/BIPOL.1988.51074\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Rink, an automatic layout verification system intended for FET technologies, has been enhanced to handle bipolar designs. A straightforward procedure that uses Rink's parasitic capacitance extractor to solve the bipolar device identification problem is described. The bipolar enhancements to Rink have been used successfully on a set of seven high-speed bipolar chips designed for lightwave communication. These chips ranged in complexity from 23 to 67 devices. Full-custom, nonmanhattan layouts for these chips were created on polygon-pusher style layout editors. For each chip, Rink executed an automatic comparison of the netlist extracted from the layout against a SPICE reference netlist. The latter has been coded for SPICE design simulations. Several fatal connectivity errors were uncovered as were a few significant disparities in resistor values and transistor sizes.<<ETX>>\",\"PeriodicalId\":302949,\"journal\":{\"name\":\"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,\",\"volume\":\"27 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1988-09-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/BIPOL.1988.51074\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BIPOL.1988.51074","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Extending an FET layout verification system to bipolar technology
Rink, an automatic layout verification system intended for FET technologies, has been enhanced to handle bipolar designs. A straightforward procedure that uses Rink's parasitic capacitance extractor to solve the bipolar device identification problem is described. The bipolar enhancements to Rink have been used successfully on a set of seven high-speed bipolar chips designed for lightwave communication. These chips ranged in complexity from 23 to 67 devices. Full-custom, nonmanhattan layouts for these chips were created on polygon-pusher style layout editors. For each chip, Rink executed an automatic comparison of the netlist extracted from the layout against a SPICE reference netlist. The latter has been coded for SPICE design simulations. Several fatal connectivity errors were uncovered as were a few significant disparities in resistor values and transistor sizes.<>
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