设计师葛量子点的奇妙世界

I-Hsiang Wang, P. Hong, K. Peng, Horng-Chih Lin, T. George, Pei-Wen Li
{"title":"设计师葛量子点的奇妙世界","authors":"I-Hsiang Wang, P. Hong, K. Peng, Horng-Chih Lin, T. George, Pei-Wen Li","doi":"10.1109/IEDM13553.2020.9372027","DOIUrl":null,"url":null,"abstract":"Starting with our remarkable discovery of spherical germanium (Ge) quantum dot (QD) formation, we have embarked on an exciting journey of further discovery, all the while maintaining CMOS-compatible processes. We have taken advantage of the many peculiar and symbiotic interactions of Si, Ge and O interstitials to create a novel portfolio of electronic, photonic and quantum computing devices. This paper summarizes several of these completely new and counter-intuitive accomplishments. Using a coordinated combination of lithographic patterning and self-assembly, size-tunable spherical Ge QDs were controllably placed at designated spatial locations within Si-containing layers. We exploited the exquisite control available through the thermal oxidation of Si1-xGex patterned structures in proximity to Si3N4/Si layers. Our so-called \"designer\" Ge QDs have succeeded in opening up myriad device possibilities, including paired QDs for qubits, single-hole transistors (SHTs) for charge sensing, photodetectors and light-emitters for Si photonics, and junctionless (JL) FETs using standard Si processing.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"The Wonderful World of Designer Ge Quantum Dots\",\"authors\":\"I-Hsiang Wang, P. Hong, K. Peng, Horng-Chih Lin, T. George, Pei-Wen Li\",\"doi\":\"10.1109/IEDM13553.2020.9372027\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Starting with our remarkable discovery of spherical germanium (Ge) quantum dot (QD) formation, we have embarked on an exciting journey of further discovery, all the while maintaining CMOS-compatible processes. We have taken advantage of the many peculiar and symbiotic interactions of Si, Ge and O interstitials to create a novel portfolio of electronic, photonic and quantum computing devices. This paper summarizes several of these completely new and counter-intuitive accomplishments. Using a coordinated combination of lithographic patterning and self-assembly, size-tunable spherical Ge QDs were controllably placed at designated spatial locations within Si-containing layers. We exploited the exquisite control available through the thermal oxidation of Si1-xGex patterned structures in proximity to Si3N4/Si layers. Our so-called \\\"designer\\\" Ge QDs have succeeded in opening up myriad device possibilities, including paired QDs for qubits, single-hole transistors (SHTs) for charge sensing, photodetectors and light-emitters for Si photonics, and junctionless (JL) FETs using standard Si processing.\",\"PeriodicalId\":415186,\"journal\":{\"name\":\"2020 IEEE International Electron Devices Meeting (IEDM)\",\"volume\":\"3 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-12-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 IEEE International Electron Devices Meeting (IEDM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM13553.2020.9372027\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE International Electron Devices Meeting (IEDM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM13553.2020.9372027","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5

摘要

从我们非凡的球形锗(Ge)量子点(QD)形成的发现开始,我们已经踏上了进一步发现的激动人心的旅程,同时保持了cmos兼容的工艺。我们利用Si, Ge和O的许多特殊的共生相互作用来创造一个新的电子,光子和量子计算设备组合。本文总结了这些全新的、反直觉的成就。利用光刻和自组装的协调组合,可调节尺寸的球形锗量子点被可控地放置在含硅层内的指定空间位置。我们利用了通过Si3N4/Si层附近的Si1-xGex图案结构的热氧化提供的精细控制。我们所谓的“设计师”Ge量子点已经成功地开辟了无数器件的可能性,包括用于量子比特的配对量子点,用于电荷传感的单孔晶体管(sht),用于硅光子学的光电探测器和发光体,以及使用标准硅处理的无结场效应管(JL)。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
The Wonderful World of Designer Ge Quantum Dots
Starting with our remarkable discovery of spherical germanium (Ge) quantum dot (QD) formation, we have embarked on an exciting journey of further discovery, all the while maintaining CMOS-compatible processes. We have taken advantage of the many peculiar and symbiotic interactions of Si, Ge and O interstitials to create a novel portfolio of electronic, photonic and quantum computing devices. This paper summarizes several of these completely new and counter-intuitive accomplishments. Using a coordinated combination of lithographic patterning and self-assembly, size-tunable spherical Ge QDs were controllably placed at designated spatial locations within Si-containing layers. We exploited the exquisite control available through the thermal oxidation of Si1-xGex patterned structures in proximity to Si3N4/Si layers. Our so-called "designer" Ge QDs have succeeded in opening up myriad device possibilities, including paired QDs for qubits, single-hole transistors (SHTs) for charge sensing, photodetectors and light-emitters for Si photonics, and junctionless (JL) FETs using standard Si processing.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Subband Engineering by Combination of Channel Thickness Scaling and (111) Surface Orientation in InAs-On-Insulator nMOSFETs A Reliability Enhanced 5nm CMOS Technology Featuring 5th Generation FinFET with Fully-Developed EUV and High Mobility Channel for Mobile SoC and High Performance Computing Application Scaling MoS2 NCFET to 83 nm with Record-low Ratio of SSave/SSRef.=0.177 and Minimum 20 mV Hysteresis Future Logic Scaling: Towards Atomic Channels and Deconstructed Chips An Improved Model on Buried-Oxide Damage for Total-Ionizing-Dose Effect on HV SOI LDMOS
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1