双栅合成WS2 mosfet，电容为120μS/μm Gm, 2.7μF/cm2，双极通道

2020 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2020-12-12 DOI:10.1109/IEDM13553.2020.9372055

D. Lin, Xiangyu Wu, D. Cott, D. Verreck, B. Groven, S. Sergeant, Q. Smets, S. Sutar, I. Asselberghs, I. Radu

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引用次数: 13

摘要

我们设计了双栅极WS2晶体管，基于表面物理吸收ALD方法，具有缩放的顶部和后门堆栈，用于高级逻辑应用。采用2ML WS2通道的双栅极MOSFET工作，在3V栅极偏置下可达到210μA/um漏极电流和2.7μF/cm2电容(>3.4×1013/cm2片电荷密度)，通断比>108，最大120μS/um。在100nm Lch下的跨导和109mV/dec亚阈值振荡。这种双栅极设计使我们能够在CVD WS2通道上探索EOT缩放，双极性I-V和C-V(电容电压)响应。

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Dual gate synthetic WS2 MOSFETs with 120μS/μm Gm 2.7μF/cm2 capacitance and ambipolar channel

We have engineered dual gate WS2 transistors with scaled top and back gate stacks based on a surface physisorption ALD approach for advanced logic applications. Connected dual gate MOSFET operation with a 2ML WS2 channel reaches 210μA/um drain current and 2.7μF/cm2 capacitance (>3.4×1013/cm2 sheet charge density) at 3V gate bias, with >108 on-off ratio, 120μS/um max. transconductance and 109mV/dec sub-threshold swing at 100nm Lch. This dual gate design enables us to explore EOT scaling, ambipolar I-V and C-V(capacitance-voltage) response on CVD WS2 channel.

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2020 IEEE International Electron Devices Meeting (IEDM)

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