A Low-Power Variable-Resolution Asynchronous Analog-to-Digital Converter

In this paper, a new power-efficient Variable Resolution Level-Crossing Analog-to-Digital Converter (LC-ADC) is proposed equipped with a regulating feedback network. The feedback network assesses the input signal activity and regulates the sampling rate continuously to prevent excessive sampling, especially for the fast-moving portions of the input signal. While the evaluation process is performed by a charge pump, another multi-level comparator and switching network are responsible for applying the results. Therefore, the quantization window is dynamically configured according to the signal activity. As a result, designing the other building blocks of the proposed LC-ADC is relaxed regarding the speed and power requirements leading to higher power efficiency. Implemented in a 0.18 μm standard CMOS process, the proposed LC-ADC occupies ~0.0041 mm2 of silicon area and consumes ~18 nW from 1 V supply voltage. Assuming a 1 kHz full-scale input sinusoidal signal, it achieves an average signal-to-noise and distortion ratio (SNDR) of ~43 dB and an effective number of bits (ENOB) of ~6.8 bits.