J. Mori, M. Nagamatsu, M. Hirano, S. Tanaka, M. Noda, Y. Toyoshima, K. Hashimoto, H. Hayashida, K. Maeguchi
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引用次数: 6
摘要
描述了一种采用双金属0.5 μ m CMOS技术制造的54倍54倍倍增器。通过采用4-2压缩器、进位选择加法器和进位前瞻加法器，实现了10-ns的乘法时间。采用54-b×54-b全阵列，在一个时延内完成乘法运算。该乘法器用于基于IEEE标准的双精度浮点数据处理，时钟范围为100mhz。该倍增器在3.62 mm * 3.45 mm的有源面积上集成了81600个晶体管
A 10 ns 54×54-bit parallel structured full array multiplier with 0.5 μm CMOS technology
A 54-b×54-b multiplier fabricated in double metal 0.5-μm CMOS technology is described. A 10-ns multiplication time has been achieved by employing a 4-2 compressor, a carry select adder, and a carry lookahead adder. The 54-b×54-b full array is adopted to complete the multiplication within one latency. This multiplier is intended for double-precision floating-point data processing based on IEEE standards up to a clock range of 100 MHz. The multiplier has integrated 81600 transistors in an active area of 3.62 mm×3.45 mm
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