设计和使用基于阵列的测试结构来表征由WLCSP焊料凸起引起的机械应力效应

2016 International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2016-03-28 DOI:10.1109/ICMTS.2016.7476175

H. Tuinhout, R. van Dalen

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引用次数: 2

摘要

本文讨论了一种基于2100- dut阵列的测试结构方法，用于高分辨率表征晶圆级芯片封装焊料凸起引起的空间机械应力分布。详细回顾了DUT单元布局要求、阵列实现、测量方法和一些数据分析挑战。焊料凹凸引起的迁移率变化的几个例子说明了这些测试结构的价值。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Design and use of an array-based test structure to characterize mechanical stress effects caused by WLCSP solder bumps

This paper discusses a 2100-DUT-array based test structure approach for high-resolution characterization of spatial mechanical stress distributions that are attributable to wafer level chip scale package solder bumps. DUT cell layout requirements, array implementation, measurement approach, and some data analysis challenges are reviewed in detail. Several examples of solder bump induced mobility variation illustrate the value of these test structures.

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2016 International Conference on Microelectronic Test Structures (ICMTS)

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