A New FPGA - based Architecture of Task Scheduler with Support of Periodic Real-Time Tasks

This paper presents a new FPGA design of a task scheduler that supports not only aperiodic hard real-time tasks but periodic tasks too. Whenever a period of a periodic task is elapsed, the task is automatically restarted with no need of software intervention. The proposed scheduler is using Earliest Deadline First (EDF) algorithm. For inter-task synchronisation, the scheduler also supports temporary suspension of tasks with automatic resumption of tasks after the specified time elapsed. The proposed architecture is based on priority queues used for time management and decision-making processes. Thanks to FPGA implementation of the scheduler and its priority queues, the scheduler operations are always performed in two clock cycles regardless of the current number of tasks and regardless of the maximum possible number of tasks in the system. The paper contains results obtained by FPGA synthesis done for various parameters using Intel FPGA Cyclone V device. The proposed solution was verified using simplified version of Universal Verification Methodology (UVM) and applying millions of test instructions with randomly generated deadline and period values.