{"title":"一种新的叶片细胞布局综合方法","authors":"M. Fukui, N. Shinomiya, T. Akino","doi":"10.1109/ASPDAC.1995.486232","DOIUrl":null,"url":null,"abstract":"We propose a new layout synthesis with 2 dimensional transistor arrangement and a spontaneous process of 2 dimensional compaction and local re routing. The compaction enables jumping over objects, minimizing the number of contacts for wiring. We applied the layout synthesis to actual cell design and obtained comparable results to hand crafted design.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"A new layout synthesis for leaf cell design\",\"authors\":\"M. Fukui, N. Shinomiya, T. Akino\",\"doi\":\"10.1109/ASPDAC.1995.486232\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We propose a new layout synthesis with 2 dimensional transistor arrangement and a spontaneous process of 2 dimensional compaction and local re routing. The compaction enables jumping over objects, minimizing the number of contacts for wiring. We applied the layout synthesis to actual cell design and obtained comparable results to hand crafted design.\",\"PeriodicalId\":119232,\"journal\":{\"name\":\"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASPDAC.1995.486232\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASPDAC.1995.486232","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
We propose a new layout synthesis with 2 dimensional transistor arrangement and a spontaneous process of 2 dimensional compaction and local re routing. The compaction enables jumping over objects, minimizing the number of contacts for wiring. We applied the layout synthesis to actual cell design and obtained comparable results to hand crafted design.