TMR的功能增强,用于节能和抗错误的ASIC设计

Hagen Sämrow, C. Cornelius, Philipp Gorski, J. Salzmann, Andreas Tockhorn, D. Timmermann
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引用次数: 2

摘要

不断发展的技术规模提高了对高效VLSI设计方法的需求,面对永久性物理缺陷的脆弱性日益增加,同时考虑到由此产生的电路实现的功率效率。三模冗余(Triple Modular Redundancy, TMR)是解决可靠性问题的常用方法,但其缺点是面积和功耗增加。这项工作介绍了一种低功率冗余(LPR)设计解决方案,针对TMR实现的功率损失。这是通过用于错误检测和操作控制的增强的和新的功能性运行时功能来实现的。通过利用TMR固有的模块化和并行性,LPR解决方案应用额外的控制逻辑在比较相位(指示故障及其位置)和并行操作(降低操作频率)之间动态切换。这允许功率优化电路操作,并完全支持永久性故障的处理。不同ALU实现的仿真结果表明,与传统TMR相比,功耗降低高达60%。此外,还介绍了在存在永久性物理缺陷的情况下实现高效节能系统运行的不同操作模式切换策略。此外,由于冗余模块的自适应使用,可靠性也得到了显著提高。
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Functional enhancements of TMR for power efficient and error resilient ASIC designs
Progressive technology scaling raises the need for efficient VLSI design methods facing the increasing vulnerability to permanent physical defects, while considering power efficiency of resulting circuit implementations at the same time. Triple Modular Redundancy (TMR) represents a common method to encounter reliability problems, but has the drawback of increased area and power consumption. This work introduces a Low Power Redundant (LPR) design solution that targets the power penalty of TMR implementations. This is done by enhanced and new functional runtime capabilities for error detection and operation control. By exploiting the inherent modularity and parallelism of TMR, the LPR solution applies additional control logic to switch dynamically between compare phases (to indicate faults and their locations) and parallel operation (with reduced operation frequency). This allows power optimized circuit operation with full support for the treatment of permanent faults. Simulation results on different ALU implementations show a decrease of power consumption of up to 60 % compared to conventional TMR. Furthermore, different strategies for the switching between operation modes are introduced that enable power efficient system operation in the presence of permanent physical defects. Moreover, significant reliability improvements are also achieved due to the adaptive use of the redundant modules.
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