7.6 k门约瑟夫逊宏细胞阵列

Digest of Technical Papers., 1990 Symposium on VLSI Circuits Pub Date : 1990-06-07 DOI:10.1109/VLSIC.1990.111099

S. Kotani, A. Inoue, S. Hasuo

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引用次数: 2

摘要

介绍了一种高速约瑟夫逊宏单元阵列的设计和技术。采用1.5 μ m Nb Josephson工艺制备了包含7.6 k栅极的macrocell阵列。芯片尺寸为5 × 5mm，功耗为23 mW。在全加法器中实现了5.3 ps的平均门延迟

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A 7.6 K-gate Josephson macrocell array

The design and technology for a high-speed Josephson macrocell array are described. A macrocell array including 7.6 k gates was fabricated using a 1.5-μm Nb Josephson process. The chip dimensions are 5×5 mm, and its power consumption is 23 mW. An average gate delay in full adder of 5.3 ps has been achieved using the macrocell

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Digest of Technical Papers., 1990 Symposium on VLSI Circuits

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