{"title":"自动帕累托分析，不断提高超大规模集成电路制造区域的工艺稳定性","authors":"T. Kielty, J. Delahunty","doi":"10.1109/ASMC.1990.111233","DOIUrl":null,"url":null,"abstract":"A software program that automatically creates Pareto diagrams which depict the most unstable electrical test parameters and the most unstable inline process parameters is discussed. The program facilitates the daily decision of which process parameter or electrical test parameter to investigate first. The Pareto diagrams provide a method for quickly determining the statistical stability for each of the process areas or the electrical test area. An implementation of the program is discussed.<<ETX>>","PeriodicalId":158760,"journal":{"name":"IEEE/SEMI Conference on Advanced Semiconductor Manufacturing Workshop","volume":"94 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Automated Pareto analysis for continuously improving a VLSI fabrication area's process stability\",\"authors\":\"T. Kielty, J. Delahunty\",\"doi\":\"10.1109/ASMC.1990.111233\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A software program that automatically creates Pareto diagrams which depict the most unstable electrical test parameters and the most unstable inline process parameters is discussed. The program facilitates the daily decision of which process parameter or electrical test parameter to investigate first. The Pareto diagrams provide a method for quickly determining the statistical stability for each of the process areas or the electrical test area. An implementation of the program is discussed.<<ETX>>\",\"PeriodicalId\":158760,\"journal\":{\"name\":\"IEEE/SEMI Conference on Advanced Semiconductor Manufacturing Workshop\",\"volume\":\"94 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-09-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE/SEMI Conference on Advanced Semiconductor Manufacturing Workshop\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASMC.1990.111233\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE/SEMI Conference on Advanced Semiconductor Manufacturing Workshop","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASMC.1990.111233","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Automated Pareto analysis for continuously improving a VLSI fabrication area's process stability
A software program that automatically creates Pareto diagrams which depict the most unstable electrical test parameters and the most unstable inline process parameters is discussed. The program facilitates the daily decision of which process parameter or electrical test parameter to investigate first. The Pareto diagrams provide a method for quickly determining the statistical stability for each of the process areas or the electrical test area. An implementation of the program is discussed.<>
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