扩频预处理器ASIC设计:一个案例研究

B. Paratore, J. C. Crichton
{"title":"扩频预处理器ASIC设计:一个案例研究","authors":"B. Paratore, J. C. Crichton","doi":"10.1109/ASIC.1990.186102","DOIUrl":null,"url":null,"abstract":"The design methodology used for development of a spread spectrum preprocessor (SSPP) is described. The SSPP in conjunction with a digital signal processor (DSP) functions as a digital demodulator for satellite communications. The key element of the design process was the combination or circuit-level and system-level functional verification. This approach ensured that the ASIC architecture supported the required DSP algorithms, and that the hardware implementation performed as intended. As a result, subtle flaws were detected early, the development was smooth, the layout was efficient, and this ASIC was a first silicon success.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Spread spectrum pre-processor ASIC design: a case study\",\"authors\":\"B. Paratore, J. C. Crichton\",\"doi\":\"10.1109/ASIC.1990.186102\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The design methodology used for development of a spread spectrum preprocessor (SSPP) is described. The SSPP in conjunction with a digital signal processor (DSP) functions as a digital demodulator for satellite communications. The key element of the design process was the combination or circuit-level and system-level functional verification. This approach ensured that the ASIC architecture supported the required DSP algorithms, and that the hardware implementation performed as intended. As a result, subtle flaws were detected early, the development was smooth, the layout was efficient, and this ASIC was a first silicon success.<<ETX>>\",\"PeriodicalId\":126693,\"journal\":{\"name\":\"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-09-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASIC.1990.186102\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1990.186102","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

摘要

介绍了扩频预处理器(SSPP)的设计方法。SSPP与数字信号处理器(DSP)一起作为卫星通信的数字解调器。设计过程的关键要素是电路级和系统级功能验证的结合。这种方法确保了ASIC架构支持所需的DSP算法,并且硬件实现按预期执行。结果,早期发现了细微的缺陷,开发顺利,布局高效,这款ASIC是第一个硅成功
本文章由计算机程序翻译,如有差异,请以英文原文为准。
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
Spread spectrum pre-processor ASIC design: a case study
The design methodology used for development of a spread spectrum preprocessor (SSPP) is described. The SSPP in conjunction with a digital signal processor (DSP) functions as a digital demodulator for satellite communications. The key element of the design process was the combination or circuit-level and system-level functional verification. This approach ensured that the ASIC architecture supported the required DSP algorithms, and that the hardware implementation performed as intended. As a result, subtle flaws were detected early, the development was smooth, the layout was efficient, and this ASIC was a first silicon success.<>
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
A development system for an SRAM-based user-reprogrammable gate array Automated CAE tools for full custom design of bipolar analog ASICs A 200 MHz 100 K ECL output buffer for CMOS ASICs Multi circular buffer controller chip for advanced ESM system Rapid prototyping, is there an educational dilemma? (ASIC design)
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1