一个2GHz, 7W(最大)64b的PowerTM微处理器核心

2007 IEEE Custom Integrated Circuits Conference Pub Date : 2007-09-01 DOI:10.1109/CICC.2007.4405833

D. Murray, J. Burnette, Brian Campbell, M. Chung, Bruce Fernandes, S. Ghosh, Rajat Goel, G. Hess, Hang Huang, Zhibin Huang, Naveen Javarappa, Pradeep Kanapathipillai, F. Klass, F. Liu, A. Mehta, Y. Modukuru, Nishant Nerurkar, Abhijit Radhakrishnan, S. Santhanam, J. Sugisawa, Shyam Sundar, Honkai John Tam, R. Wen, E. Wu, Jung-Cheng Yeh, J. Yong, S. Zambare

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引用次数: 0

摘要

PA6T核心是该电源架构的无序超标量实现。功率效率是通过微架构、逻辑和电路优化实现的。该处理器采用65nm，三Vt，双氧化物8 M CMOS工艺制造。2ghz时最坏功耗为7w。

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A 2GHz, 7W (max) 64b PowerTM Microprocessor Core

The PA6T core is an out-of-order superscalar implementation of the power architecture. Power efficiency is achieved through micro-architecture, logic, and circuit optimizations. The processor is fabricated in a 65 nm, triple Vt, dual oxide 8 M CMOS process. Worst-case power dissipation at 2 GHz is 7 W.

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2007 IEEE Custom Integrated Circuits Conference

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