{"title":"用于高级设计进入和仿真的状态机开发工具","authors":"U. Bruning, G. Radke, J. Sladky","doi":"10.1109/EURDAC.1993.410632","DOIUrl":null,"url":null,"abstract":"The design of complex hardware systems demands high level design tools in order to shorten the design time and ensure the correctness. The analysis of a typical computer design example shows that the sequential control logic of hardware systems, realized as finite state machines, is one of the major design efforts. The tools presented support the main phases of the design process for FSMs and provide a significant reduction in design time. The efficient connection to a system level simulation and the display of animated graphical FSMs by these tools are described.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"35 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"State-machine-development-tool for high-level-design entry and simulation\",\"authors\":\"U. Bruning, G. Radke, J. Sladky\",\"doi\":\"10.1109/EURDAC.1993.410632\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The design of complex hardware systems demands high level design tools in order to shorten the design time and ensure the correctness. The analysis of a typical computer design example shows that the sequential control logic of hardware systems, realized as finite state machines, is one of the major design efforts. The tools presented support the main phases of the design process for FSMs and provide a significant reduction in design time. The efficient connection to a system level simulation and the display of animated graphical FSMs by these tools are described.<<ETX>>\",\"PeriodicalId\":339176,\"journal\":{\"name\":\"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference\",\"volume\":\"35 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-09-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EURDAC.1993.410632\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EURDAC.1993.410632","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
State-machine-development-tool for high-level-design entry and simulation
The design of complex hardware systems demands high level design tools in order to shorten the design time and ensure the correctness. The analysis of a typical computer design example shows that the sequential control logic of hardware systems, realized as finite state machines, is one of the major design efforts. The tools presented support the main phases of the design process for FSMs and provide a significant reduction in design time. The efficient connection to a system level simulation and the display of animated graphical FSMs by these tools are described.<>
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