{"title":"两级OTA LHP零的新配置","authors":"M. Rashtian, Ali Najd","doi":"10.1109/IICM55040.2021.9730239","DOIUrl":null,"url":null,"abstract":"A non-Miller high bandwidth (BW) two-stage class A-AB operational transconductance amplifier (OTA) is presented. A nulling resistor with a series compensating capacitor is applied at the output node, extending the gain-bandwidth product (GBW) by introducing a left-half-plane (LHP) zero. Also, simple circuitry included an analog inverter is applied to achieve class A-AB. The proposed circuit is simulated using a $\\boldsymbol{0.18\\mu} \\mathbf{m}\\ \\boldsymbol{1.8}\\mathbf{V}$ CMOS process standard technology. Simulation results with a 10pF capacitance load show that DC gain, GBW, average SR, average 1% settling time, and phase margin (PM) are 56.0 dB, 145.2 MHz, 89.8 $\\mathbf{V}/\\mu\\mathbf{s}, \\boldsymbol{25.0}$ ns, and 58.2°, respectively. The PM, GBW, and average SR change to 79.1°,26.7 MHz, and $\\boldsymbol{17.1}\\mathbf{V}/\\boldsymbol{\\mu}\\mathbf{S}$, respectively, when driving a 100 pF capacitance load. Small signal analysis and simulation results indicate that the proposed OTA has a good performance at a large capacitive load. The proposed amplifier consumes 0.54mW @ 1.8V, which makes it a high current efficiency two-stage amplifier.","PeriodicalId":299499,"journal":{"name":"2021 Iranian International Conference on Microelectronics (IICM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A New Configuration for Two-Stage OTA LHP Zeroes\",\"authors\":\"M. Rashtian, Ali Najd\",\"doi\":\"10.1109/IICM55040.2021.9730239\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A non-Miller high bandwidth (BW) two-stage class A-AB operational transconductance amplifier (OTA) is presented. A nulling resistor with a series compensating capacitor is applied at the output node, extending the gain-bandwidth product (GBW) by introducing a left-half-plane (LHP) zero. Also, simple circuitry included an analog inverter is applied to achieve class A-AB. The proposed circuit is simulated using a $\\\\boldsymbol{0.18\\\\mu} \\\\mathbf{m}\\\\ \\\\boldsymbol{1.8}\\\\mathbf{V}$ CMOS process standard technology. Simulation results with a 10pF capacitance load show that DC gain, GBW, average SR, average 1% settling time, and phase margin (PM) are 56.0 dB, 145.2 MHz, 89.8 $\\\\mathbf{V}/\\\\mu\\\\mathbf{s}, \\\\boldsymbol{25.0}$ ns, and 58.2°, respectively. The PM, GBW, and average SR change to 79.1°,26.7 MHz, and $\\\\boldsymbol{17.1}\\\\mathbf{V}/\\\\boldsymbol{\\\\mu}\\\\mathbf{S}$, respectively, when driving a 100 pF capacitance load. Small signal analysis and simulation results indicate that the proposed OTA has a good performance at a large capacitive load. The proposed amplifier consumes 0.54mW @ 1.8V, which makes it a high current efficiency two-stage amplifier.\",\"PeriodicalId\":299499,\"journal\":{\"name\":\"2021 Iranian International Conference on Microelectronics (IICM)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-12-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 Iranian International Conference on Microelectronics (IICM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IICM55040.2021.9730239\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 Iranian International Conference on Microelectronics (IICM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IICM55040.2021.9730239","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A non-Miller high bandwidth (BW) two-stage class A-AB operational transconductance amplifier (OTA) is presented. A nulling resistor with a series compensating capacitor is applied at the output node, extending the gain-bandwidth product (GBW) by introducing a left-half-plane (LHP) zero. Also, simple circuitry included an analog inverter is applied to achieve class A-AB. The proposed circuit is simulated using a $\boldsymbol{0.18\mu} \mathbf{m}\ \boldsymbol{1.8}\mathbf{V}$ CMOS process standard technology. Simulation results with a 10pF capacitance load show that DC gain, GBW, average SR, average 1% settling time, and phase margin (PM) are 56.0 dB, 145.2 MHz, 89.8 $\mathbf{V}/\mu\mathbf{s}, \boldsymbol{25.0}$ ns, and 58.2°, respectively. The PM, GBW, and average SR change to 79.1°,26.7 MHz, and $\boldsymbol{17.1}\mathbf{V}/\boldsymbol{\mu}\mathbf{S}$, respectively, when driving a 100 pF capacitance load. Small signal analysis and simulation results indicate that the proposed OTA has a good performance at a large capacitive load. The proposed amplifier consumes 0.54mW @ 1.8V, which makes it a high current efficiency two-stage amplifier.