A high density self-aligned 4-mask planar VDMOS process

The fifth generation HEXFET technology achieves its industry leading performance by using innovative self-alignment processes to improve manufacturing precision while cutting the number of process steps. It is a scaled down form of the dominant planar DMOS technology and requires only four masks to build. The self-alignment allows junction depths and feature sizes 30-40% smaller than previous generations. This is especially critical for power FETs with voltage ratings of 100 V or below, since so much of the on-resistance is determined by the width, length, and carrier mobility of the MOS channel. The shallow base greatly reduces JFET resistance while the heavy doping reduces base resistance to enhance ruggedness.