通过减小寄生电容提高hemt集成电路的电路速度

IEEE International Electron Devices Meeting 2003 Pub Date : 2003-12-08 DOI:10.1109/IEDM.2003.1269384

K. Makiyama, T. Takahashi, T. Suzuki, K. Sawada, T. Ohki, M. Nishi, N. Hara, M. Takikawa

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引用次数: 19

摘要

我们开发了一种新的工艺技术来去除栅极周围的介电物质，以降低寄生电容。该工艺使我们能够提高集成电路的运行速度，而不会造成任何工艺损坏。因此，我们使用InP-HEMT技术实现了静态T-FF电路的90 GHz工作。这是迄今为止报道的由场效应管组成的最快的T-FF。我们还展示了这种技术在制造超高速集成电路方面的巨大潜力。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Improvement of circuit-speed of HEMTs IC by reducing the parasitic capacitance

We developed a novel process technology to removes the dielectric substance around gate electrodes to decrease parasitic capacitance. The process enabled us to increase the operating speed of the integrated circuit without causing any process damage. As a result, we achieved 90 GHz operation of a static T-FF circuit using InP-HEMT technology. This is the fastest T-FF, consisting of a FET, reported to date. We also showed the excellent potential of this technology for fabricating ultra-high speed ICs.

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IEEE International Electron Devices Meeting 2003

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