{"title":"S分栅源侧注入和0N0电荷存储堆栈(SPIN)的新型闪存器件","authors":"Wei-ming Chen, Swift, Roberts, Forbes, Higman, Maiti, Paulson, Kuo-tung Chang","doi":"10.1109/VLSIT.1997.623696","DOIUrl":null,"url":null,"abstract":"This paper discusses a novel flash memory featuring a selfaligned split gate structure with sub-0.lpm sidewall gate length, source side injection for programming, band-to-band tunneling for erasing, and an oxide/nitride/oxide (ONO) stack for charge storage. The bitcell is suitable for low voltage (1.8V) and high density (cell size 1.35 km2 using 0.4 Fm technology) applications.","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"240 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":"{\"title\":\"A Novel Flash Memory Device With S Plit Gate Source Side Injection And 0N0 Charge Storage Stack (SPIN)\",\"authors\":\"Wei-ming Chen, Swift, Roberts, Forbes, Higman, Maiti, Paulson, Kuo-tung Chang\",\"doi\":\"10.1109/VLSIT.1997.623696\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper discusses a novel flash memory featuring a selfaligned split gate structure with sub-0.lpm sidewall gate length, source side injection for programming, band-to-band tunneling for erasing, and an oxide/nitride/oxide (ONO) stack for charge storage. The bitcell is suitable for low voltage (1.8V) and high density (cell size 1.35 km2 using 0.4 Fm technology) applications.\",\"PeriodicalId\":414778,\"journal\":{\"name\":\"1997 Symposium on VLSI Technology\",\"volume\":\"240 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-06-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"12\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1997 Symposium on VLSI Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.1997.623696\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1997 Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.1997.623696","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Novel Flash Memory Device With S Plit Gate Source Side Injection And 0N0 Charge Storage Stack (SPIN)
This paper discusses a novel flash memory featuring a selfaligned split gate structure with sub-0.lpm sidewall gate length, source side injection for programming, band-to-band tunneling for erasing, and an oxide/nitride/oxide (ONO) stack for charge storage. The bitcell is suitable for low voltage (1.8V) and high density (cell size 1.35 km2 using 0.4 Fm technology) applications.
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