高密度内存模块的可测试性特性

Third Annual IEEE Proceedings on ASIC Seminar and Exhibit Pub Date : 1990-09-17 DOI:10.1109/ASIC.1990.186104

E. Parrella

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引用次数: 0

摘要

讨论了一种以硅对硅混合形式设计的可配置多芯片存储模块。在CMOS门阵列中实现的存储控制器IC也可作为存储芯片的在线测试器。这种能力，加上控制器自身的扫描路径和边界扫描功能，增加了现场可测试性，并大大降低了生产测试成本。

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Testability features in a high-density memory module

A configurable multichip memory module designed in silicon-on-silicon hybrid form is discussed. The memory controller IC, which has been implemented in a CMOS gate array, also functions as an in-circuit tester for the memory chips. This capability, supplemented by the controller's own scan-path and boundary-scan features, results in increased in-field testability as well as greatly reduced production test costs.<>

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Third Annual IEEE Proceedings on ASIC Seminar and Exhibit

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