Taegeun Yoo, T. T. Kim, Bongjin Kim, Chengshuo Yu, Kevin Chai Tshun Chuan
{"title":"用于处理神经网络的电流模式8T SRAM内存计算宏的设计","authors":"Taegeun Yoo, T. T. Kim, Bongjin Kim, Chengshuo Yu, Kevin Chai Tshun Chuan","doi":"10.1109/ISOCC50952.2020.9332992","DOIUrl":null,"url":null,"abstract":"A novel 8T SRAM bitcell is proposed for computing dot-products using current-mode accumulation. A write disturb issue has been eliminated by adding two extra transistors into a standard 6T SRAM bitcell. Besides, we embed a column ADC in each column-based neuron to address the ADC overhead issue of conventional analog compute-in-memory macros. The resolution of ADC is reconfigurable from 1 to 5bit. A test-chip is fabricated using 65nm, and the energy-efficiency of bitwise operation is 490-to-15.8TOPS/W at 1-5bit.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design of Current-Mode 8T SRAM Compute-In-Memory Macro for Processing Neural Networks\",\"authors\":\"Taegeun Yoo, T. T. Kim, Bongjin Kim, Chengshuo Yu, Kevin Chai Tshun Chuan\",\"doi\":\"10.1109/ISOCC50952.2020.9332992\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A novel 8T SRAM bitcell is proposed for computing dot-products using current-mode accumulation. A write disturb issue has been eliminated by adding two extra transistors into a standard 6T SRAM bitcell. Besides, we embed a column ADC in each column-based neuron to address the ADC overhead issue of conventional analog compute-in-memory macros. The resolution of ADC is reconfigurable from 1 to 5bit. A test-chip is fabricated using 65nm, and the energy-efficiency of bitwise operation is 490-to-15.8TOPS/W at 1-5bit.\",\"PeriodicalId\":270577,\"journal\":{\"name\":\"2020 International SoC Design Conference (ISOCC)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-10-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 International SoC Design Conference (ISOCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISOCC50952.2020.9332992\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 International SoC Design Conference (ISOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISOCC50952.2020.9332992","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of Current-Mode 8T SRAM Compute-In-Memory Macro for Processing Neural Networks
A novel 8T SRAM bitcell is proposed for computing dot-products using current-mode accumulation. A write disturb issue has been eliminated by adding two extra transistors into a standard 6T SRAM bitcell. Besides, we embed a column ADC in each column-based neuron to address the ADC overhead issue of conventional analog compute-in-memory macros. The resolution of ADC is reconfigurable from 1 to 5bit. A test-chip is fabricated using 65nm, and the energy-efficiency of bitwise operation is 490-to-15.8TOPS/W at 1-5bit.
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