Is There a need for 3D modelling for a Power Delivery Network on Package?

Power supply noise budget is scaled for High speed I/O Interfaces like PCIE-Gen5/6. The specification for power supply noise has become tighter and even variation of few mV is considered crucial for high speed I/O interfaces. Presently a 2.5D extraction tool is used for modelling Power delivery network interconnects for Package/Mother board. With data rates increasing, 2.5D tool lacks accuracy & there is a definite need for 3D modelling for improving the quality of the output to meet the ever-growing High speed I/Os (input output). Relying on 2.5D models can lead to pessimistic decoupling solution. The work in this paper mainly focuses on accurate interconnect modelling of Package/Motherboard using a 3-D field solver tool & also provides the impact on HSIO power supply noise and summarizes the need for this methodology upgrade. Also, paper discusses on how 3D PDN models helps design resources (SOC, PKG, BRD) to be optimized only to the most sensitive areas, thereby reducing the overall PDN resource cost.