{"title":"商业专用集成电路的通用设计和测试策略","authors":"E. Vopni","doi":"10.1109/ASIC.1990.186092","DOIUrl":null,"url":null,"abstract":"An approach to managing the complexities of ASIC design within a telecommunications design and manufacturing company is described. The approach is based on the use of a limited number of approved ASIC vendors, a unified multiple vendor/technology design system, centralized application support, and a central forum for information exchange. The Logic Array Design System (LADS) was developed to provide a consistent design and test methodology across multiple ASIC vendors and technologies.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A common design and test strategy for merchant ASICs\",\"authors\":\"E. Vopni\",\"doi\":\"10.1109/ASIC.1990.186092\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An approach to managing the complexities of ASIC design within a telecommunications design and manufacturing company is described. The approach is based on the use of a limited number of approved ASIC vendors, a unified multiple vendor/technology design system, centralized application support, and a central forum for information exchange. The Logic Array Design System (LADS) was developed to provide a consistent design and test methodology across multiple ASIC vendors and technologies.<<ETX>>\",\"PeriodicalId\":126693,\"journal\":{\"name\":\"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit\",\"volume\":\"7 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-09-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASIC.1990.186092\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1990.186092","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A common design and test strategy for merchant ASICs
An approach to managing the complexities of ASIC design within a telecommunications design and manufacturing company is described. The approach is based on the use of a limited number of approved ASIC vendors, a unified multiple vendor/technology design system, centralized application support, and a central forum for information exchange. The Logic Array Design System (LADS) was developed to provide a consistent design and test methodology across multiple ASIC vendors and technologies.<>
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