用于高可靠性嵌入式处理器的多比特容错寄存器文件

S. Esmaeeli, M. Hosseini, B. Vahdat, B. Rashidian
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引用次数: 10

摘要

由于微处理器在制造过程中的不断缩小,其对软误差的脆弱性越来越大。最近的研究表明,1-5%的seu(单事件扰流)会导致MBUs(多比特扰流)。由于现代技术中翻转存储位所需的最小能量降低,由于SEU而产生MBU的可能性正在增加。寄存器文件是微处理器中最敏感的元件。在本文中,我们提出了一种创新的方法来保护64位寄存器文件中的寄存器为RISC处理器使用扩展汉明(8,4)码(SEC-DED码)和窄宽度值。窄宽度值可以用寄存器宽度的一半位数表示。每个数据寄存器的两个附加位用于存储窄宽度值的信息。寄存器文件中的每个64位数据都有其独特的64位扩展汉明码,以位交错的方式存储在另一个寄存器文件中。窄宽度值的两个副本可以存储在一个寄存器中,每个副本在其他寄存器文件中都有其独特的扩展汉明码。用SPEC2000基准测试测试了该方法的故障注入仿真。在SPEC2000基准测试中,存储寄存器文件生成值并使用本文方法保护的单词的错误概率小于使用TMR或各种扩展汉明码保护的相同单词的错误概率。在Xilinx Virtex-4 FPGA上的实现表明,使用所提出的方法保护的64位宽且多于64字条目的寄存器文件的面积开销小于使用TMR保护的相同寄存器文件的面积开销。错误检测和纠正与执行阶段并行执行,以防止性能下降。该方法可对数据或扩展汉明码寄存器中相邻32位的错误进行99%以上的校正。该方法采用纯组合逻辑,可用于16位和32位的寄存器文件。
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A multi-bit error tolerant register file for a high reliable embedded processor
The vulnerability of microprocessors to soft errors is increasing due to continuous shrinking in fabrication process. Recent studies show that 1–5% of the SEUs (single event upset) can cause MBUs (multiple bit upsets). The probability of MBU generation due to SEU is increasing because of the reduction in minimum energy required to flip a memory bit in modern technologies. Register file is the most sensitive component in a microprocessor. In this paper, we present an innovative way to protect registers in a 64-bit register file for a RISC processor using extended Hamming (8, 4) code (SEC-DED code) and narrow-width values. A narrow-width value can be represented by half number of bits of the register width. Two additional bits for each data register have been used to store the information for a narrow-width value. Each 64-bit data in register file has its unique 64-bit extended Hamming code that is stored in another register file in a bit-interleaved manner. Two copies of narrow-width values can be stored in one register and each copy has its unique extended Hamming code in other register file. Proposed method has been tested using fault injection simulation with SPEC2000 benchmarks. Error probability of a word that stores generated values for register file in SPEC2000 benchmarks and is protected with proposed method is less than the error probability of the same word that is protected with TMR or various extended Hamming codes. The implementation on a Xilinx Virtex-4 FPGA shows that the area overhead of a register file with 64-bit wide and more than 64-word entry that is protected with proposed method is less than the area overhead of the same register file that is protected with TMR. Error detection and correction is performed in parallel with execute stage to prevent performance degradation. More than 99% of errors in adjacent 32 bits in data or extended Hamming code registers can be corrected with the proposed method. Presented method employs pure combinational logics and can be used for 16-bit and 32-bit register files too.
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