P. Coudrain, J. Colonna, C. Aumont, G. Garnier, P. Chausse, R. Segaud, K. Vial, A. Jouve, T. Mourier, T. Magis, P. Besson, L. Gabette, C. Brunet-Manquat, N. Allouti, C. Laviron, S. Chéramy, E. Saugier, J. Pruvost, A. Farcy, N. Hotellier
{"title":"面向高效可靠的300mm 3D技术，实现宽I/O互连","authors":"P. Coudrain, J. Colonna, C. Aumont, G. Garnier, P. Chausse, R. Segaud, K. Vial, A. Jouve, T. Mourier, T. Magis, P. Besson, L. Gabette, C. Brunet-Manquat, N. Allouti, C. Laviron, S. Chéramy, E. Saugier, J. Pruvost, A. Farcy, N. Hotellier","doi":"10.1109/EPTC.2012.6507102","DOIUrl":null,"url":null,"abstract":"This paper presents the prototype of a 3D circuit with Wide I/O interconnects in a 65nm CMOS node, assembled in a face-to-back integration and reported on a BGA. The process technology carried out for the realization of the bottom die will be presented in both 200mm and 300mm environment. Finally, the 3D assembly will be successfully assessed through electrical and reliability tests, concretising the realism of a 3D technology for future Wide I/O products.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"131 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"25","resultStr":"{\"title\":\"Towards efficient and reliable 300mm 3D technology for wide I/O interconnects\",\"authors\":\"P. Coudrain, J. Colonna, C. Aumont, G. Garnier, P. Chausse, R. Segaud, K. Vial, A. Jouve, T. Mourier, T. Magis, P. Besson, L. Gabette, C. Brunet-Manquat, N. Allouti, C. Laviron, S. Chéramy, E. Saugier, J. Pruvost, A. Farcy, N. Hotellier\",\"doi\":\"10.1109/EPTC.2012.6507102\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the prototype of a 3D circuit with Wide I/O interconnects in a 65nm CMOS node, assembled in a face-to-back integration and reported on a BGA. The process technology carried out for the realization of the bottom die will be presented in both 200mm and 300mm environment. Finally, the 3D assembly will be successfully assessed through electrical and reliability tests, concretising the realism of a 3D technology for future Wide I/O products.\",\"PeriodicalId\":431312,\"journal\":{\"name\":\"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)\",\"volume\":\"131 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"25\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EPTC.2012.6507102\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EPTC.2012.6507102","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Towards efficient and reliable 300mm 3D technology for wide I/O interconnects
This paper presents the prototype of a 3D circuit with Wide I/O interconnects in a 65nm CMOS node, assembled in a face-to-back integration and reported on a BGA. The process technology carried out for the realization of the bottom die will be presented in both 200mm and 300mm environment. Finally, the 3D assembly will be successfully assessed through electrical and reliability tests, concretising the realism of a 3D technology for future Wide I/O products.
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