Efficient Synthesis of a Uniformly Spread Layout Aware Pareto Surface for Analog Circuits

Accurate and fast optimization of analog circuits is an important requirement of current synthesis methods. Obtaining the entire pareto optimal surface for conflicting performance objectives is essential for design space exploration as well as circuit sizing. Layout parasitics prevent the circuit from realizing the estimated optimal performance values but are not considered in most existing pareto-front generation methods. We develop a layout-aware circuit matrix modeling method along with an efficient multi-objective optimizer to synthesize the parasitic inclusive pareto-optimal performance surface. The algorithm achieves a pareto surface with points spread uniformly in all regions. The sensitivity of critical performance to candidate design points is used to select the best sizing solution during synthesis. Experiments on benchmark circuits show the effectiveness of the proposed method in obtaining a speedup of an order of 10$^{3}$ with negligible loss of accuracy as compared to SPICE.