时序电路行为描述的VHDL建模与测试

Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference Pub Date : 1993-09-20 DOI:10.1109/EURDAC.1993.410674

V. Pla, J. Santucci, N. Giambiasi

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引用次数: 8

摘要

提出了一种基于VHDL行为描述形式化建模的自动测试生成原理。利用有限状态机表示和接近Petri网的形式，作者定义了两个模型来表示与VHDL描述相关的所有概念。然后，他们提出了一种同时使用前向和后向时间处理的生成原理

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On the modeling and testing of VHDL behavioral descriptions of sequential circuits

A new automatic test generation principle based on a formal modeling of VHDL behavioral descriptions is proposed. Using to the finite state machine representation and a formalism close to that of Petri nets, the authors define two models which represent all the concepts associated with a VHDL description. They then propose a generation principle which uses both forward and backward time processing.<>

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Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference

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