{"title":"数据流CPU的片上智能内存","authors":"G. Uvieghara, Y. Nakagome, D. Jeong, D. Hodges","doi":"10.1109/VLSIC.1989.1037519","DOIUrl":null,"url":null,"abstract":"Ahtract-Register Alias Table (RAT) is a smart memory that is embedded in HPSm (High-Performance Substrate), a Berkeley data-flow CPU. It is a multiport memory that has content addressability and support for branch prediction and exception handling, in addition to conventional READ and WRITE operations. An experimental 1240-bit smart memory chip is implemented in a 1.6-pm double-metal scalable CMOS process. This memory performs 15 operations within a cycle time of 100 ns, has 34 658 transistors, occupies an area of 3.8 mm X 5.2 mm, and dissipates 0.51 W I117 [a.","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"An on-chip smart memory for a data flow CPU\",\"authors\":\"G. Uvieghara, Y. Nakagome, D. Jeong, D. Hodges\",\"doi\":\"10.1109/VLSIC.1989.1037519\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Ahtract-Register Alias Table (RAT) is a smart memory that is embedded in HPSm (High-Performance Substrate), a Berkeley data-flow CPU. It is a multiport memory that has content addressability and support for branch prediction and exception handling, in addition to conventional READ and WRITE operations. An experimental 1240-bit smart memory chip is implemented in a 1.6-pm double-metal scalable CMOS process. This memory performs 15 operations within a cycle time of 100 ns, has 34 658 transistors, occupies an area of 3.8 mm X 5.2 mm, and dissipates 0.51 W I117 [a.\",\"PeriodicalId\":136228,\"journal\":{\"name\":\"Symposium 1989 on VLSI Circuits\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1989-05-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Symposium 1989 on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.1989.1037519\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Symposium 1989 on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.1989.1037519","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
摘要
RAT (Ahtract-Register Alias Table)是一种嵌入在高性能基板(HPSm)中的智能内存，HPSm是一种Berkeley数据流CPU。它是一种多端口内存，除了常规的READ和WRITE操作外，还具有内容可寻址性，并支持分支预测和异常处理。采用1.6 pm双金属可扩展CMOS工艺实现了实验性1240位智能存储芯片。该存储器在100 ns的周期时间内执行15次操作，具有34658个晶体管，占地3.8 mm X 5.2 mm，功耗为0.51 W I117 [a]。
Ahtract-Register Alias Table (RAT) is a smart memory that is embedded in HPSm (High-Performance Substrate), a Berkeley data-flow CPU. It is a multiport memory that has content addressability and support for branch prediction and exception handling, in addition to conventional READ and WRITE operations. An experimental 1240-bit smart memory chip is implemented in a 1.6-pm double-metal scalable CMOS process. This memory performs 15 operations within a cycle time of 100 ns, has 34 658 transistors, occupies an area of 3.8 mm X 5.2 mm, and dissipates 0.51 W I117 [a.
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