{"title":"分子QCA可逆1D阵列的测试","authors":"Xiaojun Ma, Jing Huang, C. Metra, F. Lombardi","doi":"10.1109/DFT.2006.63","DOIUrl":null,"url":null,"abstract":"Reversible logic design is a well-known paradigm in digital computation. While an extensive literature exists on its mathematical characterization, little work has been reported on its possible technological basis. In this paper, a quantum-dot cellular automata (QCA) is investigated for testable implementations of reversible logic. Two new reversible gates (denoted as QCA1 and QCA2) are proposed. These gates are compared (in terms of delay, area and logic synthesis) with other reversible gates (such as Toffoli and Fredkin) for QCA implementation. As the bijective nature of reversibility makes testing significantly easier than in the general case, testing of the reversible gates is pursued in detail. C-testability of a 1D array is investigated for single cell fault as well multiple cell faults. Defect analysis of the reversible gates is pursued under a single missing/additional cell assumption","PeriodicalId":113870,"journal":{"name":"2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"76 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"38","resultStr":"{\"title\":\"Testing Reversible 1D Arrays for Molecular QCA\",\"authors\":\"Xiaojun Ma, Jing Huang, C. Metra, F. Lombardi\",\"doi\":\"10.1109/DFT.2006.63\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Reversible logic design is a well-known paradigm in digital computation. While an extensive literature exists on its mathematical characterization, little work has been reported on its possible technological basis. In this paper, a quantum-dot cellular automata (QCA) is investigated for testable implementations of reversible logic. Two new reversible gates (denoted as QCA1 and QCA2) are proposed. These gates are compared (in terms of delay, area and logic synthesis) with other reversible gates (such as Toffoli and Fredkin) for QCA implementation. As the bijective nature of reversibility makes testing significantly easier than in the general case, testing of the reversible gates is pursued in detail. C-testability of a 1D array is investigated for single cell fault as well multiple cell faults. Defect analysis of the reversible gates is pursued under a single missing/additional cell assumption\",\"PeriodicalId\":113870,\"journal\":{\"name\":\"2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems\",\"volume\":\"76 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-10-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"38\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DFT.2006.63\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DFT.2006.63","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Reversible logic design is a well-known paradigm in digital computation. While an extensive literature exists on its mathematical characterization, little work has been reported on its possible technological basis. In this paper, a quantum-dot cellular automata (QCA) is investigated for testable implementations of reversible logic. Two new reversible gates (denoted as QCA1 and QCA2) are proposed. These gates are compared (in terms of delay, area and logic synthesis) with other reversible gates (such as Toffoli and Fredkin) for QCA implementation. As the bijective nature of reversibility makes testing significantly easier than in the general case, testing of the reversible gates is pursued in detail. C-testability of a 1D array is investigated for single cell fault as well multiple cell faults. Defect analysis of the reversible gates is pursued under a single missing/additional cell assumption