创新的堆叠芯片封装- S2BGA

L. Wu, Y. Wang, C. Hsiao
{"title":"创新的堆叠芯片封装- S2BGA","authors":"L. Wu, Y. Wang, C. Hsiao","doi":"10.1109/ECTC.2002.1008102","DOIUrl":null,"url":null,"abstract":"The stack-die package concept emerged 2/spl sim/3 years ago. The major product a stack-die package with flash and SRAM chips integrated together, used in cellular phones for the purpose of size and weight reduction. The basic requirement for these two dies in a stacked package is that the size difference must be large enough to allow a wire bonding process at the bottom die, if we still want to utilize the low cost, mature wire bonding technology in interconnections. However, this requirement will limit the application in trying to integrate two similar or same sized dies into a single stack-die package. One solution for this application is to utilize flip chip technology in the interconnection, to solve the die size difference requirement. One of the concerns for this package is the higher assembly cost due to flip chip interconnection. Therefore, a low cost, high reliability alternative package structure is created, it is named S2BGA (spacer stacked ball grid array). In this package, a silicon spacer is deposited between top and bottom dies to offer enough space for the wire bonding process. Since mature wire bonding technology is still utilized, a reliable and cost effective stack-die package is provided but maintains the same package size.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"Innovative stack-die package - S2BGA\",\"authors\":\"L. Wu, Y. Wang, C. Hsiao\",\"doi\":\"10.1109/ECTC.2002.1008102\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The stack-die package concept emerged 2/spl sim/3 years ago. The major product a stack-die package with flash and SRAM chips integrated together, used in cellular phones for the purpose of size and weight reduction. The basic requirement for these two dies in a stacked package is that the size difference must be large enough to allow a wire bonding process at the bottom die, if we still want to utilize the low cost, mature wire bonding technology in interconnections. However, this requirement will limit the application in trying to integrate two similar or same sized dies into a single stack-die package. One solution for this application is to utilize flip chip technology in the interconnection, to solve the die size difference requirement. One of the concerns for this package is the higher assembly cost due to flip chip interconnection. Therefore, a low cost, high reliability alternative package structure is created, it is named S2BGA (spacer stacked ball grid array). In this package, a silicon spacer is deposited between top and bottom dies to offer enough space for the wire bonding process. Since mature wire bonding technology is still utilized, a reliable and cost effective stack-die package is provided but maintains the same package size.\",\"PeriodicalId\":285713,\"journal\":{\"name\":\"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-08-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ECTC.2002.1008102\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECTC.2002.1008102","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9

摘要

堆叠芯片封装的概念在3年前就出现了。主要产品是将闪存和SRAM芯片集成在一起的堆叠芯片封装,用于手机,以减小尺寸和重量。在堆叠封装中对这两个模具的基本要求是,如果我们仍然希望在互连中利用低成本,成熟的线键合技术,则尺寸差必须足够大,以便在底部模具上进行线键合工艺。然而,这一要求将限制在试图将两个相似或相同尺寸的芯片集成到单个堆栈芯片封装中的应用。该应用的解决方案之一是在互连中利用倒装芯片技术,以解决芯片尺寸差异的要求。这种封装的一个问题是由于倒装芯片互连而导致较高的组装成本。因此,一种低成本、高可靠性的替代封装结构被创造出来,它被命名为S2BGA(间隔层堆叠球栅阵列)。在这个封装中,硅垫片沉积在顶部和底部模具之间,为线键合过程提供足够的空间。由于仍然使用成熟的线键合技术,因此提供了可靠且具有成本效益的堆栈封装,但保持了相同的封装尺寸。
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Innovative stack-die package - S2BGA
The stack-die package concept emerged 2/spl sim/3 years ago. The major product a stack-die package with flash and SRAM chips integrated together, used in cellular phones for the purpose of size and weight reduction. The basic requirement for these two dies in a stacked package is that the size difference must be large enough to allow a wire bonding process at the bottom die, if we still want to utilize the low cost, mature wire bonding technology in interconnections. However, this requirement will limit the application in trying to integrate two similar or same sized dies into a single stack-die package. One solution for this application is to utilize flip chip technology in the interconnection, to solve the die size difference requirement. One of the concerns for this package is the higher assembly cost due to flip chip interconnection. Therefore, a low cost, high reliability alternative package structure is created, it is named S2BGA (spacer stacked ball grid array). In this package, a silicon spacer is deposited between top and bottom dies to offer enough space for the wire bonding process. Since mature wire bonding technology is still utilized, a reliable and cost effective stack-die package is provided but maintains the same package size.
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