H. Hara, Yasuhiro Sugimoto, M. Noda, T. Nagamatsu, Y. Watanabe, Hiroshi Iwai, Y. Niitsu, G. Sasaki, K. Maeguchi
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A 350 ps 50 K 0.8 μm BiCMOS gate array with shared bipolar cell structure
A BiCMOS gate array with gate delay of 350 ps has been realized by 0.8-μm BiCMOS technology. Minimum gate delay and cell area have been achieved with a shared bipolar cell structure. The gate delay is almost equivalent to that of a 0.5-μm pure CMOS gate array. The cell-area increase is to only 25% compared with a 0.8-μm pure CMOS cell. I/O cells can interface with CMOS, TTL (transistor-transistor logic), and ECL (emitter-coupled logic) chips at the same time with a single supply voltage of 5 V
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