A Novel nm-grain Poly-si Gate Structure For Reduction Of Cell To Cell Write/erase Tunnel Current Deviation In High Speed Quarter Micron FLASH Memories

Using nm-thick a-Si film, we developed a novel nm-grain poly-Si gate structure for reduction of cell to cell write/erase tunnel current deviation in quarter micron FLASH memories. This gate structure is beneficial to increase tunnel current and Q,,without any degradation of the tunnel oxide reliability. These phenomena are explained by local field enhancement caused by nm-grain poly-Si interface structure. INTRODUCTION In quarter micron FLASH memories, the one of the main concerns is the way to reduce cell to cell tunnel current deviation in write or erase operation. The tunnel current locally increase at grain boundary where phosphorous concentration is locally high[l]. In accordance with scaling of FLASH memories, the grain size of poly-Si has become to be comparable to the size of tunnel area of memory cell. This situation increases the tunnel current deviation among the cells because of the decreasing number of grain boundary contained in tunnel area. To avoid this problem, minimizing the poly-Si grain size is most efficacious[2]. Fortunately, it was found that nm grain size poly-Si can be formed by annealing the nm-thick a-Si films[3]. In this case the grain size decreases with reducing a-Si film thickness. Thus, we propose a new gate structure which consist of two kinds of poly-Si layers. The lower layer is nm-grain poly-Si using ultra thin(2-l0nm) a-Si film. The upper portion poly-Si is formedwith thick a-Si film, leads to micron size grains. In this paper, we describe the electrical characteristics of tunnel oxide with nm-grain poly-Si /tunnel oxide interface. PROCESS SEQUENCE After tunnel oxide formation, ultra thin, 2-10nm thick, a-Si film was depositedat 425°C using LPCVD technique. Next, in order to form alarge grain poly-Si, 200nm thick a-Si film was deposited at 525°C. To crystallize these Si films, 900°C annealing in N2 ambient was performed for 20min., as shown in Fig.2. From the TEM observation, we found that the crystallization in lower layer begin at 800°C while upper layer crystallize easily at 600°C. As the results, nm-graidmicron grain double layer poly-Si gate structure was formedas shown in TEM results at Fig. 3. Additionally, this large grain size and flat surface of upper portion of this gate structure can provide the high reliable inter-poly dielectric films. ELECTRIC CHARACTERISTICS From the C-V measurement also from elipsometry, we found the effective tunnel oxide thickness increases with decreasing nm-grain poly-Si layer thickness(Fig.4). On the other hand, the tunneling current under same electric field increase in thinner nm-grain layer as shown in Fig.5 when the gate was negatively biased. This increase of tunnel current occurs when the nm-grain layer thickness is less than 8nm. The stress inducedleakage current(S1LC) after 8C/cmZ injection does not dependon the thickness of nm-grain layer(Fig.6,Fig.7). Thus, that this gate structure is promising in FLASH memories to increase write/erase speed without concem of retention problems. To explain these phenomena, we assumed the local electric field enhancement at the poly-Si/tunnel oxide interface. This assumption is supported by Fig. 8 which shows the FN plot from I-V measurement results. In this figure the ratio of slope B o / B represents the electric field enhancement factor[4]. When the electric field enhance locally, the value B o / B (the valueis 1.28 with thenm-grain poly-Si) shouldbegraterthan 1. We also observed tunnel oxide surface after removal of poly-Si gate by N,H.,etching using AFM. As shown in Fig.9, tunnel oxide surface with nm-grain poly-Si have roughened structure which may cause the local electric field enhancement by geometry effect[5]. On the contrary, field enhancement doesn’t cause in the case of positively biased as shown in Fig.10. In the nm-grain poly-Si/tunnel oxide structure, charge to breakdown, Qbd, increased as Fig. 11 which indicates that this structure is truly promising to FLASH memories. CONCLUSIONS Using nm-thick a-Si film, we developed a novel nm-grain poly-Si gate structure which is suitable to reduce cell to cell tunnel current deviation. This structure is promising in quarter micron high speed FLASHmemories because of the increase of tunnel current and Q,,without any degradation of the tunnel oxide reliability. These phenomena are explained by local field enhancement caused by nm-grain poly-Si interface structure. ACKNOWLEDGMENT The authors wish to thank Dr. Makoto Ohkura and Tokuo Kure for their valuable suggestions and encouragement. The authors would also like to thank Toshihiko Itoga for his fruitful discussions especially about interface structures. REFERENCES [l]M.Ushiyama, et.al., IEEEIRPS (199l)pp.3331 [2]S.Muramatsu, et.al., IEEETech. Dig. IEDM (1994)pp.847 [3]T.Ishii, et.al., Ext. Abst. of SSDM’958,p201(1995) [4]J.Yugami et.al.,Proc. IEEE ICMTS( 199 1)pp. 17 [S]J.Tanaka et.al.,Ext. Abst. of SSDM95,p240( 1995) 115 4-93081 3-75-1 /97 1997 Symposium on VLSl Technology Digest of Technical Papers