性能驱动的多源总线合成使用缓冲区插入

Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair Pub Date : 1995-08-01 DOI:10.1109/ASPDAC.1995.486234

Chia-Chun Tsai, De-Yu Kao, Chung-Kuan Cheng, Ting-Ting Y. Lin

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引用次数: 0

摘要

针对给定的多源多汇总线拓扑结构，提出了一种减少信号延迟的启发式算法。该算法通过在候选位置插入缓冲区并调整缓冲区大小来最小化延迟。实验表明，2.0、0.5和0.3微米技术的延迟分别提高了7.2%、20.7%和29.6%。

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Performance driven multiple-source bus synthesis using buffer insertion

A heuristic algorithm for a given topology of a multiple source and multiple sink bus to reduce the signal delay time is proposed. The algorithm minimizes the delay by inserting buffers into the candidate locations and sizing the buffers. Experiments show up to 7.2 %, 20.7 %, and 29.6 % improvement in delay for 2.0, 0.5, and 0.3 micron technologies, respectively.

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Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair

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