D. Neilson, B. Allen, M. Kintis, M. Hoppe, S. Maas
{"title":"一种宽带上变频集成电路","authors":"D. Neilson, B. Allen, M. Kintis, M. Hoppe, S. Maas","doi":"10.1109/MCS.1992.186026","DOIUrl":null,"url":null,"abstract":"The authors describe the design and performance of a single-chip upconverter IC consisting of a doubly balanced dual-gate FET mixer, a four-stage local oscillator (LO) amplifier, and a single-stage IF amplifier. Due to a novel mixer topology, the input passband of the converter extended from DC to 5 GHz, the LO frequency range was 8 GHz to 16 GHz, and the IF output frequency range was 8 to 10 GHz. The primary design goals for this upconverter were a high third-order intermodulation intercept point (IP/sub 3/) and good spurious-response rejection. Advanced FET models were used to optimize the circuit's intercept points. The converter exhibited an IP/sub 3/ of 23.5 dBm across most of the band; second-order intercept points (IP/sub 2/) for spurious responses were greater than +40 dBm.<<ETX>>","PeriodicalId":336288,"journal":{"name":"IEEE 1992 Microwave and Millimeter-Wave Monolithic Circuits Symposium Digest of Papers","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"A broadband upconverter IC\",\"authors\":\"D. Neilson, B. Allen, M. Kintis, M. Hoppe, S. Maas\",\"doi\":\"10.1109/MCS.1992.186026\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The authors describe the design and performance of a single-chip upconverter IC consisting of a doubly balanced dual-gate FET mixer, a four-stage local oscillator (LO) amplifier, and a single-stage IF amplifier. Due to a novel mixer topology, the input passband of the converter extended from DC to 5 GHz, the LO frequency range was 8 GHz to 16 GHz, and the IF output frequency range was 8 to 10 GHz. The primary design goals for this upconverter were a high third-order intermodulation intercept point (IP/sub 3/) and good spurious-response rejection. Advanced FET models were used to optimize the circuit's intercept points. The converter exhibited an IP/sub 3/ of 23.5 dBm across most of the band; second-order intercept points (IP/sub 2/) for spurious responses were greater than +40 dBm.<<ETX>>\",\"PeriodicalId\":336288,\"journal\":{\"name\":\"IEEE 1992 Microwave and Millimeter-Wave Monolithic Circuits Symposium Digest of Papers\",\"volume\":\"6 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1992-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE 1992 Microwave and Millimeter-Wave Monolithic Circuits Symposium Digest of Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MCS.1992.186026\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE 1992 Microwave and Millimeter-Wave Monolithic Circuits Symposium Digest of Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MCS.1992.186026","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The authors describe the design and performance of a single-chip upconverter IC consisting of a doubly balanced dual-gate FET mixer, a four-stage local oscillator (LO) amplifier, and a single-stage IF amplifier. Due to a novel mixer topology, the input passband of the converter extended from DC to 5 GHz, the LO frequency range was 8 GHz to 16 GHz, and the IF output frequency range was 8 to 10 GHz. The primary design goals for this upconverter were a high third-order intermodulation intercept point (IP/sub 3/) and good spurious-response rejection. Advanced FET models were used to optimize the circuit's intercept points. The converter exhibited an IP/sub 3/ of 23.5 dBm across most of the band; second-order intercept points (IP/sub 2/) for spurious responses were greater than +40 dBm.<>
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