高性能BiCMOS电路技术VLSI门阵列

Symposium 1989 on VLSI Circuits Pub Date : 1989-05-25 DOI:10.1109/VLSIC.1989.1037463

J. Gallia, A. Yee, K. Chau, I. Wang, W. Davis, K. Moore, B. Chas, C. Lemonds, R. Eklund, R. Havemann, T. Bonifield, J. Graham, J. Pozadzides, A. Shah

{"title":"高性能BiCMOS电路技术VLSI门阵列","authors":"J. Gallia, A. Yee, K. Chau, I. Wang, W. Davis, K. Moore, B. Chas, C. Lemonds, R. Eklund, R. Havemann, T. Bonifield, J. Graham, J. Pozadzides, A. Shah","doi":"10.1109/VLSIC.1989.1037463","DOIUrl":null,"url":null,"abstract":"BiCMOS circuits have been shown to be particularly attractive lor gate array applications because 01 ECL I/O and the high on-chip capacitance drive capabilnies. Full BiCMOS gate arrays have been introduced with densities up to 20k gates11.2.sl. However, due to bipolar size constraints, higher density arrays have been restricted to CMOS wre with BiCMOS used only in the periphery of the wre and lor ECLmL 1/0.[41","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"High performance BiCMOS circuit technology VLSI gate arrays\",\"authors\":\"J. Gallia, A. Yee, K. Chau, I. Wang, W. Davis, K. Moore, B. Chas, C. Lemonds, R. Eklund, R. Havemann, T. Bonifield, J. Graham, J. Pozadzides, A. Shah\",\"doi\":\"10.1109/VLSIC.1989.1037463\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"BiCMOS circuits have been shown to be particularly attractive lor gate array applications because 01 ECL I/O and the high on-chip capacitance drive capabilnies. Full BiCMOS gate arrays have been introduced with densities up to 20k gates11.2.sl. However, due to bipolar size constraints, higher density arrays have been restricted to CMOS wre with BiCMOS used only in the periphery of the wre and lor ECLmL 1/0.[41\",\"PeriodicalId\":136228,\"journal\":{\"name\":\"Symposium 1989 on VLSI Circuits\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1989-05-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Symposium 1989 on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.1989.1037463\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Symposium 1989 on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.1989.1037463","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 3

摘要

BiCMOS电路已被证明是特别有吸引力的门阵列应用，因为01 ECL I/O和高片上电容驱动能力。完整的BiCMOS栅极阵列已经引入，密度高达20k栅极。然而，由于双极尺寸的限制，更高密度的阵列被限制在CMOS器件中，BiCMOS仅在器件的外围和ECLmL /0中使用。[41

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High performance BiCMOS circuit technology VLSI gate arrays

BiCMOS circuits have been shown to be particularly attractive lor gate array applications because 01 ECL I/O and the high on-chip capacitance drive capabilnies. Full BiCMOS gate arrays have been introduced with densities up to 20k gates11.2.sl. However, due to bipolar size constraints, higher density arrays have been restricted to CMOS wre with BiCMOS used only in the periphery of the wre and lor ECLmL 1/0.[41

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Symposium 1989 on VLSI Circuits

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