{"title":"前馈ΔΣ调制器拓扑设计宽带通信应用","authors":"H. Daoud, S. B. Salem, S. Zouari, M. Loulou","doi":"10.1109/ICECS.2011.6122216","DOIUrl":null,"url":null,"abstract":"This paper presents a design methodology for low-distortions (feed-forward) Delta-Sigma (ΔΣ) modulators topologies used in next generations wireless applications. Thus, optimized folded cascode OTA and telescopic OTA gain-boosting are selected to implement the switched capacitor (SC) integrator. First, a second order ΔΣ modulator is implemented for 2MHz bandwidth. Second, a 2–2 cascaded ΔΣ modulator is designed for 2MHz and 10MHz bandwidths in order to improve the modulator performances. These modulators are implemented using system-level simulations as well as device-level simulations implemented with SC circuits in AMS 0.35μm CMOS process. Device-level simulations results indicate that the 2nd and the 2–2 cascaded ΔΣ modulators achieve respectively SNRs of 43dB and 38dB over bandwidths of 2MHz and 10MHz with over-sampling ratios 16 and 8.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Feed-forward ΔΣ modulators topologies design for broadband communications applications\",\"authors\":\"H. Daoud, S. B. Salem, S. Zouari, M. Loulou\",\"doi\":\"10.1109/ICECS.2011.6122216\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a design methodology for low-distortions (feed-forward) Delta-Sigma (ΔΣ) modulators topologies used in next generations wireless applications. Thus, optimized folded cascode OTA and telescopic OTA gain-boosting are selected to implement the switched capacitor (SC) integrator. First, a second order ΔΣ modulator is implemented for 2MHz bandwidth. Second, a 2–2 cascaded ΔΣ modulator is designed for 2MHz and 10MHz bandwidths in order to improve the modulator performances. These modulators are implemented using system-level simulations as well as device-level simulations implemented with SC circuits in AMS 0.35μm CMOS process. Device-level simulations results indicate that the 2nd and the 2–2 cascaded ΔΣ modulators achieve respectively SNRs of 43dB and 38dB over bandwidths of 2MHz and 10MHz with over-sampling ratios 16 and 8.\",\"PeriodicalId\":251525,\"journal\":{\"name\":\"2011 18th IEEE International Conference on Electronics, Circuits, and Systems\",\"volume\":\"11 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 18th IEEE International Conference on Electronics, Circuits, and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICECS.2011.6122216\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECS.2011.6122216","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Feed-forward ΔΣ modulators topologies design for broadband communications applications
This paper presents a design methodology for low-distortions (feed-forward) Delta-Sigma (ΔΣ) modulators topologies used in next generations wireless applications. Thus, optimized folded cascode OTA and telescopic OTA gain-boosting are selected to implement the switched capacitor (SC) integrator. First, a second order ΔΣ modulator is implemented for 2MHz bandwidth. Second, a 2–2 cascaded ΔΣ modulator is designed for 2MHz and 10MHz bandwidths in order to improve the modulator performances. These modulators are implemented using system-level simulations as well as device-level simulations implemented with SC circuits in AMS 0.35μm CMOS process. Device-level simulations results indicate that the 2nd and the 2–2 cascaded ΔΣ modulators achieve respectively SNRs of 43dB and 38dB over bandwidths of 2MHz and 10MHz with over-sampling ratios 16 and 8.