用于高速、低功耗电路应用的基于inp的hemt

1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105) Pub Date : 1998-10-21 DOI:10.1109/ICSICT.1998.785953

I. Adesida, A. Mahajan, G. Cueva

{"title":"用于高速、低功耗电路应用的基于inp的hemt","authors":"I. Adesida, A. Mahajan, G. Cueva","doi":"10.1109/ICSICT.1998.785953","DOIUrl":null,"url":null,"abstract":"Processes for the monolithic integration of enhancement- and depletion-mode HEMTs (E/D-HEMTs) in the lattice matched InP material system are described. Using the buried Pt gate technology, 0.3 /spl mu/m gate-length E-HEMTs exhibiting a threshold voltage of +167 mV and a maximum extrinsic transconductance, g/sub mext/, of 700 mS/mm are demonstrated. D-HEMTs with corresponding device parameters of -443 mV and 462 mS/mm are presented. Unity current gain cut-off frequencies of-over 95 GHz were obtained for these devices. Implementation of a divide-by-four prescaler in the direct coupled FET logic technology based on E- and D-HEMTs is demonstrated.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"InP-based HEMTs for high speed, low power circuit applications\",\"authors\":\"I. Adesida, A. Mahajan, G. Cueva\",\"doi\":\"10.1109/ICSICT.1998.785953\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Processes for the monolithic integration of enhancement- and depletion-mode HEMTs (E/D-HEMTs) in the lattice matched InP material system are described. Using the buried Pt gate technology, 0.3 /spl mu/m gate-length E-HEMTs exhibiting a threshold voltage of +167 mV and a maximum extrinsic transconductance, g/sub mext/, of 700 mS/mm are demonstrated. D-HEMTs with corresponding device parameters of -443 mV and 462 mS/mm are presented. Unity current gain cut-off frequencies of-over 95 GHz were obtained for these devices. Implementation of a divide-by-four prescaler in the direct coupled FET logic technology based on E- and D-HEMTs is demonstrated.\",\"PeriodicalId\":286980,\"journal\":{\"name\":\"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1998-10-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICSICT.1998.785953\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICSICT.1998.785953","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 3

摘要

描述了在晶格匹配的InP材料体系中增强模式和耗尽模式hemt (E/ d - hemt)的单片集成过程。采用埋入式Pt栅极技术，证明了0.3 /spl mu/m栅极长度的e- hemt具有+167 mV的阈值电压和700 mS/mm的最大外部跨导。给出了相应器件参数为-443 mV和462 mS/mm的d - hemt。这些器件获得了超过95 GHz的统一电流增益截止频率。在基于E- hemt和d - hemt的直接耦合场效应管逻辑技术中实现了一个除以4的预量器。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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InP-based HEMTs for high speed, low power circuit applications

Processes for the monolithic integration of enhancement- and depletion-mode HEMTs (E/D-HEMTs) in the lattice matched InP material system are described. Using the buried Pt gate technology, 0.3 /spl mu/m gate-length E-HEMTs exhibiting a threshold voltage of +167 mV and a maximum extrinsic transconductance, g/sub mext/, of 700 mS/mm are demonstrated. D-HEMTs with corresponding device parameters of -443 mV and 462 mS/mm are presented. Unity current gain cut-off frequencies of-over 95 GHz were obtained for these devices. Implementation of a divide-by-four prescaler in the direct coupled FET logic technology based on E- and D-HEMTs is demonstrated.

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1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)

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