Quantum simulations of electrostatics in Si cylindrical nanowire pinch-off nFETs and pFETs with a homogeneous channel including strain and arbitrary crystallographic orientations

Junctionless nanowire pinch-off FETs [1–3] are promising device structures for beyond CMOS technologies. The device is called ”junctionless” [3] because it contains a uniform doping level (n⁺ n⁺ n⁺ for nFETs or p⁺ p⁺ p⁺ for pFETs) within the whole device including source, drain, and channel, which is different from the non-uniform n⁺ pn⁺ (or p⁺ np⁺) doping profiles in conventional nMOSFETs (or pMOSFETs). Therefore, during the fabrication the doping profile in junctionless nanowire pinch-off FETs is easier to control than in the conventional MOSFET case, especially for sub-100 nm gate length devices [3]. In additions, junctionless pinch-off FETs operate similar to JFETs and inversion is not required. In order to turn off the device, a sufficiently large |VGS| is required to extend the depletion region until pinch-off occurs. This is the reason for the name ”pinch-off” FET. If the horizontal cross-section area of the nanowire is scaled, the doping level must be increased in order to keep the threshold voltage unchanged [1]. Due to the high doping levels (typically 10¹⁸ cm⁻³ to 5 × 10¹⁹ cm⁻³) the carriers are strongly influenced by ionized impurity scattering, and as a consequence, the channel effective mobility is low. Therefore, it is important to include stress/strain engineering in combination with non-standard crystallographic channel orientations to boost the transport performance of the junctionless nanowire pinch-off FET.