ACACIA: CMU模拟设计系统

1989 Proceedings of the IEEE Custom Integrated Circuits Conference Pub Date : 1989-05-15 DOI:10.1109/CICC.1989.56685

L. Carley, D. J. Garrod, R. Harjani, J. Kelly, T. Lim, Emil S. Ochotta, Rob A. Rutenbar

{"title":"ACACIA: CMU模拟设计系统","authors":"L. Carley, D. J. Garrod, R. Harjani, J. Kelly, T. Lim, Emil S. Ochotta, Rob A. Rutenbar","doi":"10.1109/CICC.1989.56685","DOIUrl":null,"url":null,"abstract":"A framework that automates the design of common analog integrated circuit modules has been developed. The framework, ACACIA, consists of three tools: OASYS, which transforms module specifications into sized schematics; ANAGRAM, which transforms sized schematics into mask geometry; and a graphics interface that facilitates automatic exploration of tradeoffs between design specifications by providing 3-D display of attainable performance surfaces","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"35","resultStr":"{\"title\":\"ACACIA: the CMU analog design system\",\"authors\":\"L. Carley, D. J. Garrod, R. Harjani, J. Kelly, T. Lim, Emil S. Ochotta, Rob A. Rutenbar\",\"doi\":\"10.1109/CICC.1989.56685\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A framework that automates the design of common analog integrated circuit modules has been developed. The framework, ACACIA, consists of three tools: OASYS, which transforms module specifications into sized schematics; ANAGRAM, which transforms sized schematics into mask geometry; and a graphics interface that facilitates automatic exploration of tradeoffs between design specifications by providing 3-D display of attainable performance surfaces\",\"PeriodicalId\":165054,\"journal\":{\"name\":\"1989 Proceedings of the IEEE Custom Integrated Circuits Conference\",\"volume\":\"16 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1989-05-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"35\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1989 Proceedings of the IEEE Custom Integrated Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.1989.56685\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.1989.56685","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 35

摘要

开发了一种通用模拟集成电路模块自动化设计框架。ACACIA框架由三个工具组成:OASYS，它将模块规范转换为大小的原理图;ANAGRAM，将大小的原理图转换成掩模几何;图形界面，通过提供可实现的性能表面的3-D显示，促进自动探索设计规范之间的权衡

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ACACIA: the CMU analog design system

A framework that automates the design of common analog integrated circuit modules has been developed. The framework, ACACIA, consists of three tools: OASYS, which transforms module specifications into sized schematics; ANAGRAM, which transforms sized schematics into mask geometry; and a graphics interface that facilitates automatic exploration of tradeoffs between design specifications by providing 3-D display of attainable performance surfaces

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1989 Proceedings of the IEEE Custom Integrated Circuits Conference

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