CDM ESD失效模式和VFTLP测试保护评估

2008 9th International Conference on Solid-State and Integrated-Circuit Technology Pub Date : 2008-12-30 DOI:10.1109/ICSICT.2008.4734539

Y. Zhou, J. Hajjar

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引用次数: 14

摘要

大多数集成电路ESD损伤是由CDM应力引起的。本文讨论了CDM的失效模式。最常见的故障是MOS器件中栅极氧化物的损坏。提出了一种利用栅极氧化物损伤监测仪和改进的VFTLP测试来评估I/O电路中CDM保护有效性和鲁棒性的新方法。本文还介绍了一种用于这种评价的测试结构。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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CDM ESD failure modes and VFTLP testing for protection evaluation

Most integrated circuit ESD damages are caused by CDM stresses. This paper discusses CDM failure modes. The most common such failure is damage to the gate oxide in the MOS device. A new methodology that uses a gate oxide damage monitor and modified VFTLP testing is proposed for assessing CDM protection effectiveness and robustness in I/O circuits. A test structure for such an evaluation is also introduced.

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2008 9th International Conference on Solid-State and Integrated-Circuit Technology

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