ASIC在线仿真器的逻辑单元仿真

S. Cravatta
{"title":"ASIC在线仿真器的逻辑单元仿真","authors":"S. Cravatta","doi":"10.1109/ASIC.1990.186118","DOIUrl":null,"url":null,"abstract":"Following a discussion of several approaches to logic cell emulation in ASIC in-circuit emulators (ICE) programmable logic components (PLCs) are selected as the recommended approach to the problem. User-programmable logic components allow ASIC ICE units to maintain flexibility through reprogrammability. Since they are reusable, PLCs inherently become cost-effective. Over the past five years PLC densities have grown four-fold, further reducing costs. Utilizing these programmable logic devices for logic cell emulation allows ASIC ICE units to provide full-chip emulation capability for use in many ASIC applications.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"86 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Logic cell emulation for ASIC in-circuit emulators\",\"authors\":\"S. Cravatta\",\"doi\":\"10.1109/ASIC.1990.186118\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Following a discussion of several approaches to logic cell emulation in ASIC in-circuit emulators (ICE) programmable logic components (PLCs) are selected as the recommended approach to the problem. User-programmable logic components allow ASIC ICE units to maintain flexibility through reprogrammability. Since they are reusable, PLCs inherently become cost-effective. Over the past five years PLC densities have grown four-fold, further reducing costs. Utilizing these programmable logic devices for logic cell emulation allows ASIC ICE units to provide full-chip emulation capability for use in many ASIC applications.<<ETX>>\",\"PeriodicalId\":126693,\"journal\":{\"name\":\"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit\",\"volume\":\"86 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-09-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASIC.1990.186118\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1990.186118","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

摘要

在讨论了几种在ASIC电路仿真器(ICE)中实现逻辑单元仿真的方法之后,本文选择了可编程逻辑元件(plc)作为解决该问题的推荐方法。用户可编程逻辑组件允许ASIC ICE单元通过可重新编程来保持灵活性。由于它们是可重复使用的,plc本身就具有成本效益。在过去的五年中,PLC的密度增长了四倍,进一步降低了成本。利用这些可编程逻辑器件进行逻辑单元仿真,允许ASIC ICE单元提供全芯片仿真功能,用于许多ASIC应用程序。
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Logic cell emulation for ASIC in-circuit emulators
Following a discussion of several approaches to logic cell emulation in ASIC in-circuit emulators (ICE) programmable logic components (PLCs) are selected as the recommended approach to the problem. User-programmable logic components allow ASIC ICE units to maintain flexibility through reprogrammability. Since they are reusable, PLCs inherently become cost-effective. Over the past five years PLC densities have grown four-fold, further reducing costs. Utilizing these programmable logic devices for logic cell emulation allows ASIC ICE units to provide full-chip emulation capability for use in many ASIC applications.<>
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