一个2 ns 16 K ECL RAM，降低了字线电压波动

Digest of Technical Papers., 1990 Symposium on VLSI Circuits Pub Date : 1990-06-07 DOI:10.1109/VLSIC.1990.111088

Y. Nakase, T. Ikeda, K. Mashiko, S. Kayano

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引用次数: 2

摘要

为了实现高速ECL(发射极耦合逻辑)ram，提出了一种减字线电压摆幅电路。这使得在不牺牲写操作的情况下，字线电压波动很小，并且可以获得快25%的读操作。在电路中，为了实现快速的写入操作，需要较大的ISR和较小的反向模式电流增益

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A 2 ns 16 K ECL RAM with reduced word line voltage swing

A reduced word line voltage swing circuit is proposed in order to achieve high-speed ECL (emitter coupled logic) RAMs. This makes the word line voltage swing small without any sacrifice of the write operation, and allows 25% faster read operation to be obtained. In the circuit, large ISR and small reverse mode current gain are required for the fast write operation

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Digest of Technical Papers., 1990 Symposium on VLSI Circuits

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