C. Zota, C. Convertino, Y. Baumgartner, M. Sousa, D. Caimi, L. Czornomaz
{"title":"高性能量子阱InGaAs-On-Si mosfet,栅极长度低于20nm,用于射频应用","authors":"C. Zota, C. Convertino, Y. Baumgartner, M. Sousa, D. Caimi, L. Czornomaz","doi":"10.1109/IEDM.2018.8614530","DOIUrl":null,"url":null,"abstract":"We demonstrate RF-compatible quantum well InGaAs MOSFETs integrated on Si substrates, with <tex>$L_{\\mathrm{G}}$</tex> down to 14 nm and a Si CMOS compatible RMG fabrication flow. Devices exhibit simultaneously extrapolated <tex>$f_{\\mathrm{t}}$</tex> and <tex>$f_{\\max}$</tex> of 370 and 310 GHz, respectively, the highest reported combined <tex>$f_{\\mathrm{t}}/f_{\\max}$</tex> for III-V MOSFETs on Si. This is enabled by the scaled <tex>$L_{\\mathrm{G}},\\ g_{\\mathrm{m}}$</tex> of <tex>$1.75\\ \\text{mS}/\\mu \\mathrm{n}$</tex>, 8 nm source and drain spacers and raised source and drain extensions maintaining low access resistance. The use of the InP/In<inf>0.75</inf>Ga<inf>0.25</inf>As/InP quantum well offers three times higher electron mobility and a 60% increase of <tex>$g_{\\mathrm{m}}$</tex>, compared to reference devices.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"18","resultStr":"{\"title\":\"High Performance Quantum Well InGaAs-On-Si MOSFETs With sub-20 nm Gate Length For RF Applications\",\"authors\":\"C. Zota, C. Convertino, Y. Baumgartner, M. Sousa, D. Caimi, L. Czornomaz\",\"doi\":\"10.1109/IEDM.2018.8614530\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We demonstrate RF-compatible quantum well InGaAs MOSFETs integrated on Si substrates, with <tex>$L_{\\\\mathrm{G}}$</tex> down to 14 nm and a Si CMOS compatible RMG fabrication flow. Devices exhibit simultaneously extrapolated <tex>$f_{\\\\mathrm{t}}$</tex> and <tex>$f_{\\\\max}$</tex> of 370 and 310 GHz, respectively, the highest reported combined <tex>$f_{\\\\mathrm{t}}/f_{\\\\max}$</tex> for III-V MOSFETs on Si. This is enabled by the scaled <tex>$L_{\\\\mathrm{G}},\\\\ g_{\\\\mathrm{m}}$</tex> of <tex>$1.75\\\\ \\\\text{mS}/\\\\mu \\\\mathrm{n}$</tex>, 8 nm source and drain spacers and raised source and drain extensions maintaining low access resistance. The use of the InP/In<inf>0.75</inf>Ga<inf>0.25</inf>As/InP quantum well offers three times higher electron mobility and a 60% increase of <tex>$g_{\\\\mathrm{m}}$</tex>, compared to reference devices.\",\"PeriodicalId\":152963,\"journal\":{\"name\":\"2018 IEEE International Electron Devices Meeting (IEDM)\",\"volume\":\"6 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"18\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE International Electron Devices Meeting (IEDM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.2018.8614530\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE International Electron Devices Meeting (IEDM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2018.8614530","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 18
摘要
我们展示了集成在Si衬底上的rf兼容量子阱InGaAs mosfet, $L_{\mathrm{G}}$低至14 nm,并具有Si CMOS兼容的RMG制造流程。器件同时外推$f_{\mathrm{t}}$和$f_{\max}$分别为370 GHz和310 GHz,这是硅基III-V mosfet的最高报道组合$f_{\mathrm{t}}/f_{\max}$。这是通过$1.75\ \text{mS}/\mu \mathrm{n}$的缩放$L_{\mathrm{G}},\ g_{\mathrm{m}}$, 8纳米源极和漏极隔离器以及提高源极和漏极扩展来实现的,以保持低访问电阻。使用InP/In0.75Ga0.25As/InP量子阱提供了三倍高的电子迁移率和60% increase of $g_{\mathrm{m}}$, compared to reference devices.
High Performance Quantum Well InGaAs-On-Si MOSFETs With sub-20 nm Gate Length For RF Applications
We demonstrate RF-compatible quantum well InGaAs MOSFETs integrated on Si substrates, with $L_{\mathrm{G}}$ down to 14 nm and a Si CMOS compatible RMG fabrication flow. Devices exhibit simultaneously extrapolated $f_{\mathrm{t}}$ and $f_{\max}$ of 370 and 310 GHz, respectively, the highest reported combined $f_{\mathrm{t}}/f_{\max}$ for III-V MOSFETs on Si. This is enabled by the scaled $L_{\mathrm{G}},\ g_{\mathrm{m}}$ of $1.75\ \text{mS}/\mu \mathrm{n}$, 8 nm source and drain spacers and raised source and drain extensions maintaining low access resistance. The use of the InP/In0.75Ga0.25As/InP quantum well offers three times higher electron mobility and a 60% increase of $g_{\mathrm{m}}$, compared to reference devices.