采用65nm CMOS技术的高效率双电源64kB L1高速缓存

2007 IEEE Custom Integrated Circuits Conference Pub Date : 2007-09-01 DOI:10.1109/CICC.2007.4405834

Brian Campbell, J. Burnette, Naveen Javarappa, V. V. Kaenel

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引用次数: 4

摘要

PA6T-1682M SoC CPU上的64kb LI缓存由65 nm CMOS工艺制造的常见数据和标签结构组成，在2 GHz时提供1.5周期的读取延迟和32 GB/s带宽。优化缓存性能和功耗的几个功能包括断电安全电平移位器、流线型双电源位片、细粒度时钟门控和集中式标签平面图。

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Power-Efficient Dual-Supply 64kB L1 Caches in a 65nm CMOS Technology

The 64 kB LI caches on the PA6T-1682M SoC CPU are composed of common data and tag structures fabricated in a 65 nm CMOS process and deliver a 1.5 cycle read latency with 32 GB/s bandwidth at 2 GHz. Several features optimize cache performance and power including power-down safe level shifters, streamlined dual-supply bitslices, fine-grain clock gating, and a centralized tag floorplan.

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2007 IEEE Custom Integrated Circuits Conference

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