{"title":"用离散对数变换求低功率模整数幂","authors":"M. Byers, J. Di","doi":"10.1109/MNRC.2008.4683391","DOIUrl":null,"url":null,"abstract":"Exponentiation is an important mathematical operation in many areas, and is constantly being researched for more efficient methods. This paper presents a power efficient implementation of integer modular exponentiation using discrete logarithm transformation. By transforming the base of an exponent, this method is able to perform modular exponentiation without the use of multipliers. Originally developed and implemented for high speed applications, this method has been modified and implemented for low power while maintaining comparable performance. The design is created and simulated with a repeative-square design for comparison purpose. The two circuits are compared in terms of speed and power consumption. Results show that for bus sizes greater than 32 bit, the proposed design is able to use only approximately 40% of the power that the repeative-square counterpart consumes.","PeriodicalId":247684,"journal":{"name":"2008 1st Microsystems and Nanoelectronics Research Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Low power modular integer exponentiation using discrete logarithm transformation\",\"authors\":\"M. Byers, J. Di\",\"doi\":\"10.1109/MNRC.2008.4683391\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Exponentiation is an important mathematical operation in many areas, and is constantly being researched for more efficient methods. This paper presents a power efficient implementation of integer modular exponentiation using discrete logarithm transformation. By transforming the base of an exponent, this method is able to perform modular exponentiation without the use of multipliers. Originally developed and implemented for high speed applications, this method has been modified and implemented for low power while maintaining comparable performance. The design is created and simulated with a repeative-square design for comparison purpose. The two circuits are compared in terms of speed and power consumption. Results show that for bus sizes greater than 32 bit, the proposed design is able to use only approximately 40% of the power that the repeative-square counterpart consumes.\",\"PeriodicalId\":247684,\"journal\":{\"name\":\"2008 1st Microsystems and Nanoelectronics Research Conference\",\"volume\":\"16 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-11-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 1st Microsystems and Nanoelectronics Research Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MNRC.2008.4683391\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 1st Microsystems and Nanoelectronics Research Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MNRC.2008.4683391","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Low power modular integer exponentiation using discrete logarithm transformation
Exponentiation is an important mathematical operation in many areas, and is constantly being researched for more efficient methods. This paper presents a power efficient implementation of integer modular exponentiation using discrete logarithm transformation. By transforming the base of an exponent, this method is able to perform modular exponentiation without the use of multipliers. Originally developed and implemented for high speed applications, this method has been modified and implemented for low power while maintaining comparable performance. The design is created and simulated with a repeative-square design for comparison purpose. The two circuits are compared in terms of speed and power consumption. Results show that for bus sizes greater than 32 bit, the proposed design is able to use only approximately 40% of the power that the repeative-square counterpart consumes.