B. Bhaumik, Pravas Pradhan, G. Visweswaran, Rajamohan Varambally, Anand Hardi
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In this paper a low power SRAM design is presented. Existing SRAM architectures used in SGS Thomson were studied to explore the possibilities in bringing down power dissipation in various blocks. A Divided word line (DWL) scheme was implemented. Particular emphasis was put to reduce power consumption in decoders. A new critical path model was introduced for schematic simulation. This lowered the simulation time considerably. Simulation results confirmed the effectiveness of our approach.
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