基于0.13 μm CMOS的3.3 gbps位串行块交错最小和LDPC解码器

2007 IEEE Custom Integrated Circuits Conference Pub Date : 2007-09-01 DOI:10.1109/CICC.2007.4405773

Ahmad Darabiha, A. C. Carusone, F. Kschischang

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引用次数: 56

摘要

提出了一种用于多gbps LDPC译码的位串行结构，以缓解LDPC译码器的路由拥塞问题。我们报告了一个3.3 gbps 0.13 μm CMOS原型。它的核心面积为7.3 mm2，最大功耗为1416mw，采用1.2 v电源。我们演示了如何提前终止和电源电压缩放可以提高解码器的能量效率。最后，将相同的架构应用于符合10GBase-T标准的(2048,1723)LDPC代码。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 3.3-Gbps bit-serial block-interlaced min-sum LDPC decoder in 0.13-μm CMOS

A bit-serial architecture for multi-Gbps LDPC decoding is demonstrated to alleviate the routing congestion which is the main limitation for LDPC decoders. We report on a 3.3-Gbps 0.13-μm CMOS prototype. It occupies 7.3-mm2 core area with 1416-mW maximum power consumption from a 1.2-V supply. We demonstrate how early termination and supply voltage scaling can improve the decoder energy efficiency. Finally, the same architecture is applied to a (2048, 1723) LDPC code compliant with the 10GBase-T standard.

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2007 IEEE Custom Integrated Circuits Conference

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