具有512K字节辅助缓存的基于奔腾的CPU模块的时钟考虑

R.M. Reinschmidt, D. Leuthold
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引用次数: 3

摘要

设计并实现了一种基于pentium处理器模块的时钟分配方法。多个时钟驱动器输出并联连接,并通过串联端接电阻驱动PC板走线到模块的输入端。在模块上,20个骰子的时钟输入连接在一起,并带到单个PGA引脚。确定了终端电阻、压脉板箔特性阻抗和箔长度对时钟波形特性的影响,包括偏度、边缘率、超调和飞行时间
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Clocking considerations for a Pentium-based CPU module with 512K byte secondary cache
A method of distributing clock to and on a Pentium-based CPU module was designed and produced. Multiple clock driver outputs are connected in parallel and drive a PC board trace through a series termination resistor to the input of the module. On the module, the clock inputs to 20 dice are connected together and brought to a single PGA pin. The effect of varying termination resistance, PWB foil characteristic impedance, and foil length on the clock waveform characteristics including skew, edge rate, overshoot, and time of flight were determined.<>
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