功耗为25mw的12位5 μ s CMOS递归ADC

1989 Proceedings of the IEEE Custom Integrated Circuits Conference Pub Date : 1989-05-15 DOI:10.1109/CICC.1989.56713

M. Yotsuyanagi, A. Yukawa, K. Hino-oka, K. Shiraki, H. Abiko

{"title":"功耗为25mw的12位5 μ s CMOS递归ADC","authors":"M. Yotsuyanagi, A. Yukawa, K. Hino-oka, K. Shiraki, H. Abiko","doi":"10.1109/CICC.1989.56713","DOIUrl":null,"url":null,"abstract":"A 12-bit 5-μs CMOS analog-to-digital converter (ADC) has been realized in a 4-mm2 area with power consumption of only 25 mW ADC with 25 mW at a supply voltage of 5 V. Trimming and software calibration were not used. A four-step recursive subranging architecture has been adopted","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"70 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A 12 bit 5 μsec CMOS recursive ADC with 25 mW power consumption\",\"authors\":\"M. Yotsuyanagi, A. Yukawa, K. Hino-oka, K. Shiraki, H. Abiko\",\"doi\":\"10.1109/CICC.1989.56713\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 12-bit 5-μs CMOS analog-to-digital converter (ADC) has been realized in a 4-mm2 area with power consumption of only 25 mW ADC with 25 mW at a supply voltage of 5 V. Trimming and software calibration were not used. A four-step recursive subranging architecture has been adopted\",\"PeriodicalId\":165054,\"journal\":{\"name\":\"1989 Proceedings of the IEEE Custom Integrated Circuits Conference\",\"volume\":\"70 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1989-05-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1989 Proceedings of the IEEE Custom Integrated Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.1989.56713\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.1989.56713","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 4

摘要

一种12位5 μs CMOS模数转换器(ADC)在4 mm2的面积内实现，功耗仅为25 mW，电源电压为5 V时功耗为25 mW。没有使用修剪和软件校准。采用了四步递归子分区结构

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A 12 bit 5 μsec CMOS recursive ADC with 25 mW power consumption

A 12-bit 5-μs CMOS analog-to-digital converter (ADC) has been realized in a 4-mm2 area with power consumption of only 25 mW ADC with 25 mW at a supply voltage of 5 V. Trimming and software calibration were not used. A four-step recursive subranging architecture has been adopted

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1989 Proceedings of the IEEE Custom Integrated Circuits Conference

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