采用FRAM微阵列架构的384ns唤醒时间的零泄漏微控制器

Sudhanshu Khanna, Steven Bartling, M. Clinton, S. Summerfelt, John A. Rodriguez, H. McAdams
{"title":"采用FRAM微阵列架构的384ns唤醒时间的零泄漏微控制器","authors":"Sudhanshu Khanna, Steven Bartling, M. Clinton, S. Summerfelt, John A. Rodriguez, H. McAdams","doi":"10.1109/ASSCC.2013.6690972","DOIUrl":null,"url":null,"abstract":"Catalog ULP microcontrollers (MCUs) have to balance the needs of diverse customers by providing high performance along with near zero standby power and fast wakeup times for real time applications. We present a full HVT 8MHz 75uA/MHz Non-Volatile Logic (NVL) based MCU that has zero standby power and an ultrafast 384ns wakeup time. Non-volatile mini-arrays distributed throughout the logic domain of the MCU snapshot the state of all sequential elements before the MCU goes into a power gated standby mode. Upon wakeup no bootup is required. A high bandwidth parallel connection between the flipflops and mini-arrays helps achieve fast MCU wakeup. NVL has no impact on MCU active mode performance and power and adds only 3.6% to the SoC area. By eliminating leakage in standby mode, NVL allows use of high performance leaky processes in MCU design. We present results from a second generation full SVT 32MHz NVL MCU. The SVT SoC has 4x higher active mode performance or 30% lower active energy than the HVT SoC, but can still achieve zero leakage using NVL.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Zero leakage microcontroller with 384ns wakeup time using FRAM mini-array architecture\",\"authors\":\"Sudhanshu Khanna, Steven Bartling, M. Clinton, S. Summerfelt, John A. Rodriguez, H. McAdams\",\"doi\":\"10.1109/ASSCC.2013.6690972\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Catalog ULP microcontrollers (MCUs) have to balance the needs of diverse customers by providing high performance along with near zero standby power and fast wakeup times for real time applications. We present a full HVT 8MHz 75uA/MHz Non-Volatile Logic (NVL) based MCU that has zero standby power and an ultrafast 384ns wakeup time. Non-volatile mini-arrays distributed throughout the logic domain of the MCU snapshot the state of all sequential elements before the MCU goes into a power gated standby mode. Upon wakeup no bootup is required. A high bandwidth parallel connection between the flipflops and mini-arrays helps achieve fast MCU wakeup. NVL has no impact on MCU active mode performance and power and adds only 3.6% to the SoC area. By eliminating leakage in standby mode, NVL allows use of high performance leaky processes in MCU design. We present results from a second generation full SVT 32MHz NVL MCU. The SVT SoC has 4x higher active mode performance or 30% lower active energy than the HVT SoC, but can still achieve zero leakage using NVL.\",\"PeriodicalId\":296544,\"journal\":{\"name\":\"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)\",\"volume\":\"23 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-12-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASSCC.2013.6690972\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2013.6690972","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3

摘要

目录ULP微控制器(mcu)必须通过为实时应用提供高性能以及接近零的待机功率和快速唤醒时间来平衡不同客户的需求。我们提出了一个全HVT 8MHz 75uA/MHz基于非易失性逻辑(NVL)的MCU,具有零待机功率和超快的384ns唤醒时间。在MCU进入电源门控待机模式之前,分布在整个MCU逻辑域的非易失性微型阵列快照所有顺序元件的状态。在唤醒时,不需要启动。触发器和微型阵列之间的高带宽并行连接有助于实现快速MCU唤醒。NVL对MCU有源模式性能和功率没有影响,仅增加了3.6%的SoC面积。通过消除待机模式下的泄漏,NVL允许在MCU设计中使用高性能泄漏工艺。我们介绍了第二代全SVT 32MHz NVL MCU的结果。SVT SoC的有源模式性能比HVT SoC高4倍,有源能量比HVT SoC低30%,但使用NVL仍然可以实现零泄漏。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
Zero leakage microcontroller with 384ns wakeup time using FRAM mini-array architecture
Catalog ULP microcontrollers (MCUs) have to balance the needs of diverse customers by providing high performance along with near zero standby power and fast wakeup times for real time applications. We present a full HVT 8MHz 75uA/MHz Non-Volatile Logic (NVL) based MCU that has zero standby power and an ultrafast 384ns wakeup time. Non-volatile mini-arrays distributed throughout the logic domain of the MCU snapshot the state of all sequential elements before the MCU goes into a power gated standby mode. Upon wakeup no bootup is required. A high bandwidth parallel connection between the flipflops and mini-arrays helps achieve fast MCU wakeup. NVL has no impact on MCU active mode performance and power and adds only 3.6% to the SoC area. By eliminating leakage in standby mode, NVL allows use of high performance leaky processes in MCU design. We present results from a second generation full SVT 32MHz NVL MCU. The SVT SoC has 4x higher active mode performance or 30% lower active energy than the HVT SoC, but can still achieve zero leakage using NVL.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Future mobile society beyond Moore's Law A 691 Mbps 1.392mm2 configurable radix-16 turbo decoder ASIC for 3GPP-LTE and WiMAX systems in 65nm CMOS Collaborative innovation for future mobile applications A 0.5V 34.4uW 14.28kfps 105dB smart image sensor with array-level analog signal processing An 85mW 14-bit 150MS/s pipelined ADC with 71.3dB peak SNDR in 130nm CMOS
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1